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[/] [pci/] [tags/] [asyst_3] - Rev 92

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Rev Log message Author Age Path
92 Update! mihad 7736d 09h /pci/tags/asyst_3
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7771d 23h /pci/tags/asyst_3
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7771d 23h /pci/tags/asyst_3
89 Burst 2 error fixed. mihad 7807d 23h /pci/tags/asyst_3
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7813d 22h /pci/tags/asyst_3
87 Updated acording to RTL changes. mihad 7825d 20h /pci/tags/asyst_3
86 Entered the option to disable no response counter in wb master. mihad 7825d 20h /pci/tags/asyst_3
85 Changed Vendor ID defines. mihad 7826d 00h /pci/tags/asyst_3
84 Changed vendor ID. mihad 7829d 18h /pci/tags/asyst_3
83 Cleaned up the code. No functional changes. mihad 7854d 17h /pci/tags/asyst_3
81 Updated synchronization in top level fifo modules. mihad 7868d 13h /pci/tags/asyst_3
79 Updated. mihad 7871d 18h /pci/tags/asyst_3
78 Old files with wrong names removed. mihad 7871d 19h /pci/tags/asyst_3
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7871d 19h /pci/tags/asyst_3
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7874d 18h /pci/tags/asyst_3
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7877d 19h /pci/tags/asyst_3
73 Bug fixes, testcases added. mihad 7877d 19h /pci/tags/asyst_3
72 *** empty log message *** mihad 7924d 23h /pci/tags/asyst_3
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7932d 15h /pci/tags/asyst_3
69 Changed BIST signal names etc.. mihad 7969d 22h /pci/tags/asyst_3
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7973d 08h /pci/tags/asyst_3
67 Changed BIST signals for RAMs. tadejm 7973d 13h /pci/tags/asyst_3
66 Changed empty status generation in pciw_fifo_control.v mihad 7976d 23h /pci/tags/asyst_3
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7979d 21h /pci/tags/asyst_3
64 The testcase I just added in previous revision repaired mihad 7979d 23h /pci/tags/asyst_3
63 Added additional testcase and changed rst name in BIST to trst mihad 7980d 01h /pci/tags/asyst_3
62 Added BIST signals for RAMs. mihad 7982d 18h /pci/tags/asyst_3
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7990d 18h /pci/tags/asyst_3
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7990d 19h /pci/tags/asyst_3
58 Removed all logic from asynchronous reset network mihad 7995d 20h /pci/tags/asyst_3

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