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[/] [pci/] [tags/] [rel_10] - Rev 83

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Rev Log message Author Age Path
83 Cleaned up the code. No functional changes. mihad 7823d 20h /pci/tags/rel_10
81 Updated synchronization in top level fifo modules. mihad 7837d 17h /pci/tags/rel_10
79 Updated. mihad 7840d 22h /pci/tags/rel_10
78 Old files with wrong names removed. mihad 7840d 22h /pci/tags/rel_10
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7840d 22h /pci/tags/rel_10
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7843d 22h /pci/tags/rel_10
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7846d 22h /pci/tags/rel_10
73 Bug fixes, testcases added. mihad 7846d 23h /pci/tags/rel_10
72 *** empty log message *** mihad 7894d 03h /pci/tags/rel_10
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7901d 18h /pci/tags/rel_10
69 Changed BIST signal names etc.. mihad 7939d 02h /pci/tags/rel_10
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7942d 11h /pci/tags/rel_10
67 Changed BIST signals for RAMs. tadejm 7942d 16h /pci/tags/rel_10
66 Changed empty status generation in pciw_fifo_control.v mihad 7946d 02h /pci/tags/rel_10
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7949d 01h /pci/tags/rel_10
64 The testcase I just added in previous revision repaired mihad 7949d 03h /pci/tags/rel_10
63 Added additional testcase and changed rst name in BIST to trst mihad 7949d 05h /pci/tags/rel_10
62 Added BIST signals for RAMs. mihad 7951d 22h /pci/tags/rel_10
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7959d 21h /pci/tags/rel_10
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7959d 23h /pci/tags/rel_10
58 Removed all logic from asynchronous reset network mihad 7964d 23h /pci/tags/rel_10
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7965d 05h /pci/tags/rel_10
56 Number of state bits define was removed mihad 7965d 20h /pci/tags/rel_10
55 Changed state machine encoding to true one-hot mihad 7965d 20h /pci/tags/rel_10
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7998d 22h /pci/tags/rel_10
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7999d 01h /pci/tags/rel_10
52 Oops, never before noticed that OC header is missing mihad 7999d 06h /pci/tags/rel_10
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7999d 06h /pci/tags/rel_10
50 Got rid of undef directives mihad 8001d 22h /pci/tags/rel_10
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8001d 22h /pci/tags/rel_10

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