URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10] - Rev 93

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
93	Added a test application!	mihad	7705d 11h	/pci/tags/rel_10
92	Update!	mihad	7705d 11h	/pci/tags/rel_10
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7741d 01h	/pci/tags/rel_10
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7741d 01h	/pci/tags/rel_10
89	Burst 2 error fixed.	mihad	7777d 02h	/pci/tags/rel_10
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7783d 01h	/pci/tags/rel_10
87	Updated acording to RTL changes.	mihad	7794d 22h	/pci/tags/rel_10
86	Entered the option to disable no response counter in wb master.	mihad	7794d 22h	/pci/tags/rel_10
85	Changed Vendor ID defines.	mihad	7795d 03h	/pci/tags/rel_10
84	Changed vendor ID.	mihad	7798d 21h	/pci/tags/rel_10
83	Cleaned up the code. No functional changes.	mihad	7823d 19h	/pci/tags/rel_10
81	Updated synchronization in top level fifo modules.	mihad	7837d 16h	/pci/tags/rel_10
79	Updated.	mihad	7840d 21h	/pci/tags/rel_10
78	Old files with wrong names removed.	mihad	7840d 21h	/pci/tags/rel_10
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7840d 21h	/pci/tags/rel_10
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7843d 21h	/pci/tags/rel_10
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7846d 21h	/pci/tags/rel_10
73	Bug fixes, testcases added.	mihad	7846d 22h	/pci/tags/rel_10
72	* empty log message *	mihad	7894d 01h	/pci/tags/rel_10
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7901d 17h	/pci/tags/rel_10
69	Changed BIST signal names etc..	mihad	7939d 01h	/pci/tags/rel_10
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7942d 10h	/pci/tags/rel_10
67	Changed BIST signals for RAMs.	tadejm	7942d 15h	/pci/tags/rel_10
66	Changed empty status generation in pciw_fifo_control.v	mihad	7946d 01h	/pci/tags/rel_10
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7949d 00h	/pci/tags/rel_10
64	The testcase I just added in previous revision repaired	mihad	7949d 02h	/pci/tags/rel_10
63	Added additional testcase and changed rst name in BIST to trst	mihad	7949d 04h	/pci/tags/rel_10
62	Added BIST signals for RAMs.	mihad	7951d 21h	/pci/tags/rel_10
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7959d 20h	/pci/tags/rel_10
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7959d 22h	/pci/tags/rel_10

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10] - Rev 93

Filtering Options