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[/] [pci/] [tags/] [rel_11/] [bench] - Rev 104

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Rev Log message Author Age Path
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7722d 01h /pci/tags/rel_11/bench
92 Update! mihad 7769d 07h /pci/tags/rel_11/bench
89 Burst 2 error fixed. mihad 7840d 21h /pci/tags/rel_11/bench
87 Updated acording to RTL changes. mihad 7858d 18h /pci/tags/rel_11/bench
81 Updated synchronization in top level fifo modules. mihad 7901d 11h /pci/tags/rel_11/bench
73 Bug fixes, testcases added. mihad 7910d 17h /pci/tags/rel_11/bench
69 Changed BIST signal names etc.. mihad 8002d 20h /pci/tags/rel_11/bench
66 Changed empty status generation in pciw_fifo_control.v mihad 8009d 21h /pci/tags/rel_11/bench
64 The testcase I just added in previous revision repaired mihad 8012d 21h /pci/tags/rel_11/bench
63 Added additional testcase and changed rst name in BIST to trst mihad 8012d 23h /pci/tags/rel_11/bench
62 Added BIST signals for RAMs. mihad 8015d 16h /pci/tags/rel_11/bench
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8028d 23h /pci/tags/rel_11/bench
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8062d 16h /pci/tags/rel_11/bench
52 Oops, never before noticed that OC header is missing mihad 8063d 00h /pci/tags/rel_11/bench
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8063d 00h /pci/tags/rel_11/bench
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8071d 22h /pci/tags/rel_11/bench
44 Added for testing of Configuration Cycles Type 1 mihad 8071d 23h /pci/tags/rel_11/bench
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8071d 23h /pci/tags/rel_11/bench
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8217d 02h /pci/tags/rel_11/bench
34 Added missing include statements mihad 8232d 00h /pci/tags/rel_11/bench
33 Added some testcases, removed un-needed fifo signals mihad 8232d 21h /pci/tags/rel_11/bench
26 Modified testbench and fixed some bugs mihad 8246d 17h /pci/tags/rel_11/bench
19 *** empty log message *** mihad 8264d 18h /pci/tags/rel_11/bench
15 Initial testbench import. Still under development mihad 8264d 20h /pci/tags/rel_11/bench
3 New project directory structure mihad 8386d 17h /pci/tags/rel_11/bench

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