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[/] [pci/] [tags/] [rel_12/] - Rev 76

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Rev Log message Author Age Path
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7845d 00h /pci/tags/rel_12
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7848d 01h /pci/tags/rel_12
73 Bug fixes, testcases added. mihad 7848d 01h /pci/tags/rel_12
72 *** empty log message *** mihad 7895d 05h /pci/tags/rel_12
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7902d 21h /pci/tags/rel_12
69 Changed BIST signal names etc.. mihad 7940d 04h /pci/tags/rel_12
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7943d 14h /pci/tags/rel_12
67 Changed BIST signals for RAMs. tadejm 7943d 19h /pci/tags/rel_12
66 Changed empty status generation in pciw_fifo_control.v mihad 7947d 05h /pci/tags/rel_12
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7950d 03h /pci/tags/rel_12
64 The testcase I just added in previous revision repaired mihad 7950d 05h /pci/tags/rel_12
63 Added additional testcase and changed rst name in BIST to trst mihad 7950d 07h /pci/tags/rel_12
62 Added BIST signals for RAMs. mihad 7953d 00h /pci/tags/rel_12
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7961d 00h /pci/tags/rel_12
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7961d 01h /pci/tags/rel_12
58 Removed all logic from asynchronous reset network mihad 7966d 02h /pci/tags/rel_12
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7966d 08h /pci/tags/rel_12
56 Number of state bits define was removed mihad 7966d 22h /pci/tags/rel_12
55 Changed state machine encoding to true one-hot mihad 7966d 23h /pci/tags/rel_12
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8000d 00h /pci/tags/rel_12
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8000d 04h /pci/tags/rel_12
52 Oops, never before noticed that OC header is missing mihad 8000d 08h /pci/tags/rel_12
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8000d 08h /pci/tags/rel_12
50 Got rid of undef directives mihad 8003d 01h /pci/tags/rel_12
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8003d 01h /pci/tags/rel_12
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8003d 01h /pci/tags/rel_12
47 Known issues repaired mihad 8003d 06h /pci/tags/rel_12
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8008d 01h /pci/tags/rel_12
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8009d 06h /pci/tags/rel_12
44 Added for testing of Configuration Cycles Type 1 mihad 8009d 07h /pci/tags/rel_12

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