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[/] [pci/] [tags/] [rel_12/] [apps] - Rev 97

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Rev Log message Author Age Path
97 Doing a little bit of cleanup. mihad 7735d 14h /pci/tags/rel_12/apps
96 Update! mihad 7735d 14h /pci/tags/rel_12/apps
93 Added a test application! mihad 7735d 21h /pci/tags/rel_12/apps
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7771d 12h /pci/tags/rel_12/apps
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7771d 12h /pci/tags/rel_12/apps
85 Changed Vendor ID defines. mihad 7825d 13h /pci/tags/rel_12/apps
84 Changed vendor ID. mihad 7829d 08h /pci/tags/rel_12/apps
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7871d 08h /pci/tags/rel_12/apps
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7874d 07h /pci/tags/rel_12/apps
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7877d 08h /pci/tags/rel_12/apps
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7990d 08h /pci/tags/rel_12/apps
38 This file is not needed tadej 8129d 09h /pci/tags/rel_12/apps
36 *** empty log message *** tadej 8129d 09h /pci/tags/rel_12/apps
31 User defined constants used for Test Application tadej 8210d 04h /pci/tags/rel_12/apps
29 Xilinx synthesys log file tadej 8210d 15h /pci/tags/rel_12/apps
25 *** empty log message *** mihad 8231d 06h /pci/tags/rel_12/apps
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8231d 09h /pci/tags/rel_12/apps
14 *** empty log message *** mihad 8231d 11h /pci/tags/rel_12/apps
5 Added .o file for kernel 2.4.3 mihad 8353d 07h /pci/tags/rel_12/apps
3 New project directory structure mihad 8353d 08h /pci/tags/rel_12/apps
2 New project directory structure mihad 8353d 09h /pci/tags/rel_12/apps

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