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[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 124

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Rev Log message Author Age Path
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7571d 17h /pci/tags/rel_12/rtl
122 mbist signals updated according to newest convention markom 7578d 17h /pci/tags/rel_12/rtl
117 WB Master is now WISHBONE B3 compatible. tadejm 7635d 05h /pci/tags/rel_12/rtl
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7635d 05h /pci/tags/rel_12/rtl
115 Added signals for WB Master B3. tadejm 7635d 06h /pci/tags/rel_12/rtl
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7642d 08h /pci/tags/rel_12/rtl
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7642d 13h /pci/tags/rel_12/rtl
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7644d 12h /pci/tags/rel_12/rtl
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7648d 10h /pci/tags/rel_12/rtl
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7653d 08h /pci/tags/rel_12/rtl
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7658d 18h /pci/tags/rel_12/rtl
94 Changed one critical PCI bus signal logic. mihad 7705d 16h /pci/tags/rel_12/rtl
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7783d 13h /pci/tags/rel_12/rtl
86 Entered the option to disable no response counter in wb master. mihad 7795d 11h /pci/tags/rel_12/rtl
83 Cleaned up the code. No functional changes. mihad 7824d 08h /pci/tags/rel_12/rtl
81 Updated synchronization in top level fifo modules. mihad 7838d 04h /pci/tags/rel_12/rtl
79 Updated. mihad 7841d 09h /pci/tags/rel_12/rtl
78 Old files with wrong names removed. mihad 7841d 09h /pci/tags/rel_12/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7841d 09h /pci/tags/rel_12/rtl
73 Bug fixes, testcases added. mihad 7847d 10h /pci/tags/rel_12/rtl
72 *** empty log message *** mihad 7894d 14h /pci/tags/rel_12/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7902d 06h /pci/tags/rel_12/rtl
69 Changed BIST signal names etc.. mihad 7939d 13h /pci/tags/rel_12/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7942d 23h /pci/tags/rel_12/rtl
67 Changed BIST signals for RAMs. tadejm 7943d 03h /pci/tags/rel_12/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 7946d 14h /pci/tags/rel_12/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7949d 12h /pci/tags/rel_12/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 7949d 16h /pci/tags/rel_12/rtl
62 Added BIST signals for RAMs. mihad 7952d 09h /pci/tags/rel_12/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7960d 09h /pci/tags/rel_12/rtl

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