OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog] - Rev 73

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 Bug fixes, testcases added. mihad 7906d 11h /pci/tags/rel_3/rtl/verilog
72 *** empty log message *** mihad 7953d 15h /pci/tags/rel_3/rtl/verilog
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7961d 06h /pci/tags/rel_3/rtl/verilog
69 Changed BIST signal names etc.. mihad 7998d 14h /pci/tags/rel_3/rtl/verilog
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8001d 23h /pci/tags/rel_3/rtl/verilog
67 Changed BIST signals for RAMs. tadejm 8002d 04h /pci/tags/rel_3/rtl/verilog
66 Changed empty status generation in pciw_fifo_control.v mihad 8005d 15h /pci/tags/rel_3/rtl/verilog
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8008d 13h /pci/tags/rel_3/rtl/verilog
63 Added additional testcase and changed rst name in BIST to trst mihad 8008d 17h /pci/tags/rel_3/rtl/verilog
62 Added BIST signals for RAMs. mihad 8011d 10h /pci/tags/rel_3/rtl/verilog
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8019d 10h /pci/tags/rel_3/rtl/verilog
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8019d 11h /pci/tags/rel_3/rtl/verilog
58 Removed all logic from asynchronous reset network mihad 8024d 11h /pci/tags/rel_3/rtl/verilog
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8024d 17h /pci/tags/rel_3/rtl/verilog
56 Number of state bits define was removed mihad 8025d 08h /pci/tags/rel_3/rtl/verilog
55 Changed state machine encoding to true one-hot mihad 8025d 09h /pci/tags/rel_3/rtl/verilog
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8058d 14h /pci/tags/rel_3/rtl/verilog
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8058d 18h /pci/tags/rel_3/rtl/verilog
50 Got rid of undef directives mihad 8061d 10h /pci/tags/rel_3/rtl/verilog
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8061d 10h /pci/tags/rel_3/rtl/verilog
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8061d 10h /pci/tags/rel_3/rtl/verilog
47 Known issues repaired mihad 8061d 16h /pci/tags/rel_3/rtl/verilog
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8066d 10h /pci/tags/rel_3/rtl/verilog
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8067d 16h /pci/tags/rel_3/rtl/verilog
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8212d 19h /pci/tags/rel_3/rtl/verilog
33 Added some testcases, removed un-needed fifo signals mihad 8228d 15h /pci/tags/rel_3/rtl/verilog
32 Added include statement that was missing and causing errors mihad 8236d 12h /pci/tags/rel_3/rtl/verilog
26 Modified testbench and fixed some bugs mihad 8242d 11h /pci/tags/rel_3/rtl/verilog
23 *** empty log message *** mihad 8260d 11h /pci/tags/rel_3/rtl/verilog
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8260d 12h /pci/tags/rel_3/rtl/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.