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[/] [pci/] [tags/] [rel_4/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5633d 20h /pci/tags/rel_4
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7867d 11h /tags/rel_4
79 Updated. mihad 7867d 11h /trunk
78 Old files with wrong names removed. mihad 7867d 11h /trunk
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7867d 11h /trunk
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7870d 11h /trunk
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7873d 12h /trunk
73 Bug fixes, testcases added. mihad 7873d 12h /trunk
72 *** empty log message *** mihad 7920d 16h /trunk
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7928d 08h /trunk
69 Changed BIST signal names etc.. mihad 7965d 15h /trunk
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7969d 01h /trunk
67 Changed BIST signals for RAMs. tadejm 7969d 05h /trunk
66 Changed empty status generation in pciw_fifo_control.v mihad 7972d 16h /trunk
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7975d 14h /trunk
64 The testcase I just added in previous revision repaired mihad 7975d 16h /trunk
63 Added additional testcase and changed rst name in BIST to trst mihad 7975d 18h /trunk
62 Added BIST signals for RAMs. mihad 7978d 11h /trunk
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7986d 11h /trunk
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7986d 12h /trunk
58 Removed all logic from asynchronous reset network mihad 7991d 12h /trunk
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7991d 18h /trunk
56 Number of state bits define was removed mihad 7992d 09h /trunk
55 Changed state machine encoding to true one-hot mihad 7992d 10h /trunk
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8025d 11h /trunk
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8025d 15h /trunk
52 Oops, never before noticed that OC header is missing mihad 8025d 19h /trunk
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8025d 19h /trunk
50 Got rid of undef directives mihad 8028d 11h /trunk
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8028d 11h /trunk

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