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[/] [pci/] [tags/] [rel_4/] - Rev 71

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Rev	Log message	Author	Age	Path
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7927d 15h	/pci/tags/rel_4
69	Changed BIST signal names etc..	mihad	7964d 23h	/pci/tags/rel_4
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7968d 08h	/pci/tags/rel_4
67	Changed BIST signals for RAMs.	tadejm	7968d 13h	/pci/tags/rel_4
66	Changed empty status generation in pciw_fifo_control.v	mihad	7971d 23h	/pci/tags/rel_4
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7974d 21h	/pci/tags/rel_4
64	The testcase I just added in previous revision repaired	mihad	7975d 00h	/pci/tags/rel_4
63	Added additional testcase and changed rst name in BIST to trst	mihad	7975d 02h	/pci/tags/rel_4
62	Added BIST signals for RAMs.	mihad	7977d 18h	/pci/tags/rel_4
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7985d 18h	/pci/tags/rel_4
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7985d 20h	/pci/tags/rel_4
58	Removed all logic from asynchronous reset network	mihad	7990d 20h	/pci/tags/rel_4
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7991d 02h	/pci/tags/rel_4
56	Number of state bits define was removed	mihad	7991d 17h	/pci/tags/rel_4
55	Changed state machine encoding to true one-hot	mihad	7991d 17h	/pci/tags/rel_4
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8024d 19h	/pci/tags/rel_4
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8024d 22h	/pci/tags/rel_4
52	Oops, never before noticed that OC header is missing	mihad	8025d 02h	/pci/tags/rel_4
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8025d 03h	/pci/tags/rel_4
50	Got rid of undef directives	mihad	8027d 19h	/pci/tags/rel_4
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8027d 19h	/pci/tags/rel_4
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8027d 19h	/pci/tags/rel_4
47	Known issues repaired	mihad	8028d 01h	/pci/tags/rel_4
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8032d 19h	/pci/tags/rel_4
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8034d 01h	/pci/tags/rel_4
44	Added for testing of Configuration Cycles Type 1	mihad	8034d 01h	/pci/tags/rel_4
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8034d 01h	/pci/tags/rel_4
42	Removed out of date files	mihad	8046d 02h	/pci/tags/rel_4
40	From these Wrod files PDF were created - added future improvements	tadej	8124d 16h	/pci/tags/rel_4
39	File not needed	tadej	8124d 17h	/pci/tags/rel_4

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[/] [pci/] [tags/] [rel_4/] - Rev 71

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