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[/] [pci/] [tags/] [rel_5/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5586d 09h /pci/tags/rel_5
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7816d 19h /tags/rel_5
81 Updated synchronization in top level fifo modules. mihad 7816d 19h /trunk
79 Updated. mihad 7820d 00h /trunk
78 Old files with wrong names removed. mihad 7820d 01h /trunk
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7820d 01h /trunk
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7823d 00h /trunk
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7826d 01h /trunk
73 Bug fixes, testcases added. mihad 7826d 01h /trunk
72 *** empty log message *** mihad 7873d 05h /trunk
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7880d 21h /trunk
69 Changed BIST signal names etc.. mihad 7918d 04h /trunk
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7921d 14h /trunk
67 Changed BIST signals for RAMs. tadejm 7921d 19h /trunk
66 Changed empty status generation in pciw_fifo_control.v mihad 7925d 05h /trunk
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7928d 03h /trunk
64 The testcase I just added in previous revision repaired mihad 7928d 05h /trunk
63 Added additional testcase and changed rst name in BIST to trst mihad 7928d 07h /trunk
62 Added BIST signals for RAMs. mihad 7931d 00h /trunk
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7939d 00h /trunk
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7939d 01h /trunk
58 Removed all logic from asynchronous reset network mihad 7944d 02h /trunk
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7944d 08h /trunk
56 Number of state bits define was removed mihad 7944d 22h /trunk
55 Changed state machine encoding to true one-hot mihad 7944d 23h /trunk
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7978d 01h /trunk
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7978d 04h /trunk
52 Oops, never before noticed that OC header is missing mihad 7978d 08h /trunk
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7978d 08h /trunk
50 Got rid of undef directives mihad 7981d 01h /trunk

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