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[/] [pci/] [tags/] [rel_5/] [bench/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5649d 07h /pci/tags/rel_5/bench/verilog
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7879d 18h /pci/tags/rel_5/bench/verilog
81 Updated synchronization in top level fifo modules. mihad 7879d 18h /pci/tags/rel_5/bench/verilog
73 Bug fixes, testcases added. mihad 7889d 00h /pci/tags/rel_5/bench/verilog
69 Changed BIST signal names etc.. mihad 7981d 03h /pci/tags/rel_5/bench/verilog
66 Changed empty status generation in pciw_fifo_control.v mihad 7988d 03h /pci/tags/rel_5/bench/verilog
64 The testcase I just added in previous revision repaired mihad 7991d 04h /pci/tags/rel_5/bench/verilog
63 Added additional testcase and changed rst name in BIST to trst mihad 7991d 06h /pci/tags/rel_5/bench/verilog
62 Added BIST signals for RAMs. mihad 7993d 22h /pci/tags/rel_5/bench/verilog
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8007d 06h /pci/tags/rel_5/bench/verilog
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8040d 23h /pci/tags/rel_5/bench/verilog
52 Oops, never before noticed that OC header is missing mihad 8041d 06h /pci/tags/rel_5/bench/verilog
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8041d 07h /pci/tags/rel_5/bench/verilog
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8050d 05h /pci/tags/rel_5/bench/verilog
44 Added for testing of Configuration Cycles Type 1 mihad 8050d 05h /pci/tags/rel_5/bench/verilog
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8050d 05h /pci/tags/rel_5/bench/verilog
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8195d 08h /pci/tags/rel_5/bench/verilog
34 Added missing include statements mihad 8210d 07h /pci/tags/rel_5/bench/verilog
33 Added some testcases, removed un-needed fifo signals mihad 8211d 04h /pci/tags/rel_5/bench/verilog
26 Modified testbench and fixed some bugs mihad 8224d 23h /pci/tags/rel_5/bench/verilog
19 *** empty log message *** mihad 8243d 01h /pci/tags/rel_5/bench/verilog
15 Initial testbench import. Still under development mihad 8243d 02h /pci/tags/rel_5/bench/verilog
3 New project directory structure mihad 8365d 00h /pci/tags/rel_5/bench/verilog

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