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[/] [pci/] [tags/] [rel_6/] [sim/] [rtl_sim/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5588d 21h /pci/tags/rel_6/sim/rtl_sim
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7623d 16h /pci/tags/rel_6/sim/rtl_sim
109 There was missing path to hdl.var file. tadejm 7629d 13h /pci/tags/rel_6/sim/rtl_sim
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7634d 11h /pci/tags/rel_6/sim/rtl_sim
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7639d 21h /pci/tags/rel_6/sim/rtl_sim
95 Removed this file, because it was too large - long download time. mihad 7686d 19h /pci/tags/rel_6/sim/rtl_sim
92 Update! mihad 7687d 03h /pci/tags/rel_6/sim/rtl_sim
81 Updated synchronization in top level fifo modules. mihad 7819d 07h /pci/tags/rel_6/sim/rtl_sim
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7822d 12h /pci/tags/rel_6/sim/rtl_sim
73 Bug fixes, testcases added. mihad 7828d 13h /pci/tags/rel_6/sim/rtl_sim
72 *** empty log message *** mihad 7875d 17h /pci/tags/rel_6/sim/rtl_sim
63 Added additional testcase and changed rst name in BIST to trst mihad 7930d 19h /pci/tags/rel_6/sim/rtl_sim
62 Added BIST signals for RAMs. mihad 7933d 12h /pci/tags/rel_6/sim/rtl_sim
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7941d 12h /pci/tags/rel_6/sim/rtl_sim
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7941d 13h /pci/tags/rel_6/sim/rtl_sim
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7980d 20h /pci/tags/rel_6/sim/rtl_sim
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7983d 12h /pci/tags/rel_6/sim/rtl_sim
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7989d 18h /pci/tags/rel_6/sim/rtl_sim
42 Removed out of date files mihad 8001d 19h /pci/tags/rel_6/sim/rtl_sim
30 Example of PCI testbench log file mihad 8161d 17h /pci/tags/rel_6/sim/rtl_sim
27 Modified testbench and fixed some bugs mihad 8164d 12h /pci/tags/rel_6/sim/rtl_sim
26 Modified testbench and fixed some bugs mihad 8164d 13h /pci/tags/rel_6/sim/rtl_sim
22 Added short description for simulation running mihad 8182d 13h /pci/tags/rel_6/sim/rtl_sim
17 *** empty log message *** mihad 8182d 15h /pci/tags/rel_6/sim/rtl_sim
16 Import of various scripts for simulation running mihad 8182d 15h /pci/tags/rel_6/sim/rtl_sim

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