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[/] [pci/] [tags/] [rel_7/] - Rev 87

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Rev Log message Author Age Path
87 Updated acording to RTL changes. mihad 7813d 17h /pci/tags/rel_7
86 Entered the option to disable no response counter in wb master. mihad 7813d 17h /pci/tags/rel_7
85 Changed Vendor ID defines. mihad 7813d 21h /pci/tags/rel_7
84 Changed vendor ID. mihad 7817d 15h /pci/tags/rel_7
83 Cleaned up the code. No functional changes. mihad 7842d 14h /pci/tags/rel_7
81 Updated synchronization in top level fifo modules. mihad 7856d 10h /pci/tags/rel_7
79 Updated. mihad 7859d 15h /pci/tags/rel_7
78 Old files with wrong names removed. mihad 7859d 15h /pci/tags/rel_7
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7859d 15h /pci/tags/rel_7
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7862d 15h /pci/tags/rel_7
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7865d 16h /pci/tags/rel_7
73 Bug fixes, testcases added. mihad 7865d 16h /pci/tags/rel_7
72 *** empty log message *** mihad 7912d 20h /pci/tags/rel_7
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7920d 12h /pci/tags/rel_7
69 Changed BIST signal names etc.. mihad 7957d 19h /pci/tags/rel_7
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7961d 05h /pci/tags/rel_7
67 Changed BIST signals for RAMs. tadejm 7961d 09h /pci/tags/rel_7
66 Changed empty status generation in pciw_fifo_control.v mihad 7964d 20h /pci/tags/rel_7
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7967d 18h /pci/tags/rel_7
64 The testcase I just added in previous revision repaired mihad 7967d 20h /pci/tags/rel_7
63 Added additional testcase and changed rst name in BIST to trst mihad 7967d 22h /pci/tags/rel_7
62 Added BIST signals for RAMs. mihad 7970d 15h /pci/tags/rel_7
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7978d 15h /pci/tags/rel_7
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7978d 16h /pci/tags/rel_7
58 Removed all logic from asynchronous reset network mihad 7983d 16h /pci/tags/rel_7
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7983d 22h /pci/tags/rel_7
56 Number of state bits define was removed mihad 7984d 13h /pci/tags/rel_7
55 Changed state machine encoding to true one-hot mihad 7984d 14h /pci/tags/rel_7
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8017d 15h /pci/tags/rel_7
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8017d 19h /pci/tags/rel_7

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