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[/] [pci/] [tags/] [rel_7/] [rtl] - Rev 108

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Rev	Log message	Author	Age	Path
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7673d 22h	/pci/tags/rel_7/rtl
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7678d 21h	/pci/tags/rel_7/rtl
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7684d 07h	/pci/tags/rel_7/rtl
94	Changed one critical PCI bus signal logic.	mihad	7731d 05h	/pci/tags/rel_7/rtl
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7809d 02h	/pci/tags/rel_7/rtl
86	Entered the option to disable no response counter in wb master.	mihad	7821d 00h	/pci/tags/rel_7/rtl
83	Cleaned up the code. No functional changes.	mihad	7849d 21h	/pci/tags/rel_7/rtl
81	Updated synchronization in top level fifo modules.	mihad	7863d 17h	/pci/tags/rel_7/rtl
79	Updated.	mihad	7866d 22h	/pci/tags/rel_7/rtl
78	Old files with wrong names removed.	mihad	7866d 22h	/pci/tags/rel_7/rtl
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7866d 22h	/pci/tags/rel_7/rtl
73	Bug fixes, testcases added.	mihad	7872d 23h	/pci/tags/rel_7/rtl
72	* empty log message *	mihad	7920d 03h	/pci/tags/rel_7/rtl
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7927d 18h	/pci/tags/rel_7/rtl
69	Changed BIST signal names etc..	mihad	7965d 02h	/pci/tags/rel_7/rtl
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7968d 11h	/pci/tags/rel_7/rtl
67	Changed BIST signals for RAMs.	tadejm	7968d 16h	/pci/tags/rel_7/rtl
66	Changed empty status generation in pciw_fifo_control.v	mihad	7972d 03h	/pci/tags/rel_7/rtl
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7975d 01h	/pci/tags/rel_7/rtl
63	Added additional testcase and changed rst name in BIST to trst	mihad	7975d 05h	/pci/tags/rel_7/rtl
62	Added BIST signals for RAMs.	mihad	7977d 22h	/pci/tags/rel_7/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7985d 22h	/pci/tags/rel_7/rtl
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7985d 23h	/pci/tags/rel_7/rtl
58	Removed all logic from asynchronous reset network	mihad	7990d 23h	/pci/tags/rel_7/rtl
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7991d 05h	/pci/tags/rel_7/rtl
56	Number of state bits define was removed	mihad	7991d 20h	/pci/tags/rel_7/rtl
55	Changed state machine encoding to true one-hot	mihad	7991d 21h	/pci/tags/rel_7/rtl
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8025d 02h	/pci/tags/rel_7/rtl
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8025d 06h	/pci/tags/rel_7/rtl
50	Got rid of undef directives	mihad	8027d 22h	/pci/tags/rel_7/rtl

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[/] [pci/] [tags/] [rel_7/] [rtl] - Rev 108

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