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[/] [pci/] [tags/] [rel_8/] [bench/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5588d 01h /pci/tags/rel_8/bench
120 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7615d 13h /pci/tags/rel_8/bench
119 Added support for WB B3. Some testcases were updated. tadejm 7615d 13h /pci/tags/rel_8/bench
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7628d 17h /pci/tags/rel_8/bench
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7633d 15h /pci/tags/rel_8/bench
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7639d 01h /pci/tags/rel_8/bench
92 Update! mihad 7686d 07h /pci/tags/rel_8/bench
89 Burst 2 error fixed. mihad 7757d 21h /pci/tags/rel_8/bench
87 Updated acording to RTL changes. mihad 7775d 18h /pci/tags/rel_8/bench
81 Updated synchronization in top level fifo modules. mihad 7818d 12h /pci/tags/rel_8/bench
73 Bug fixes, testcases added. mihad 7827d 17h /pci/tags/rel_8/bench
69 Changed BIST signal names etc.. mihad 7919d 20h /pci/tags/rel_8/bench
66 Changed empty status generation in pciw_fifo_control.v mihad 7926d 21h /pci/tags/rel_8/bench
64 The testcase I just added in previous revision repaired mihad 7929d 21h /pci/tags/rel_8/bench
63 Added additional testcase and changed rst name in BIST to trst mihad 7929d 23h /pci/tags/rel_8/bench
62 Added BIST signals for RAMs. mihad 7932d 16h /pci/tags/rel_8/bench
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7946d 00h /pci/tags/rel_8/bench
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7979d 17h /pci/tags/rel_8/bench
52 Oops, never before noticed that OC header is missing mihad 7980d 00h /pci/tags/rel_8/bench
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7980d 00h /pci/tags/rel_8/bench
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7988d 22h /pci/tags/rel_8/bench
44 Added for testing of Configuration Cycles Type 1 mihad 7988d 23h /pci/tags/rel_8/bench
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7988d 23h /pci/tags/rel_8/bench
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8134d 02h /pci/tags/rel_8/bench
34 Added missing include statements mihad 8149d 00h /pci/tags/rel_8/bench
33 Added some testcases, removed un-needed fifo signals mihad 8149d 22h /pci/tags/rel_8/bench
26 Modified testbench and fixed some bugs mihad 8163d 17h /pci/tags/rel_8/bench
19 *** empty log message *** mihad 8181d 18h /pci/tags/rel_8/bench
15 Initial testbench import. Still under development mihad 8181d 20h /pci/tags/rel_8/bench
3 New project directory structure mihad 8303d 18h /pci/tags/rel_8/bench

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