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[/] [pci/] [tags/] [rel_8/] [rtl/] [verilog/] - Rev 83

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Rev Log message Author Age Path
83 Cleaned up the code. No functional changes. mihad 7853d 16h /pci/tags/rel_8/rtl/verilog
81 Updated synchronization in top level fifo modules. mihad 7867d 12h /pci/tags/rel_8/rtl/verilog
79 Updated. mihad 7870d 17h /pci/tags/rel_8/rtl/verilog
78 Old files with wrong names removed. mihad 7870d 17h /pci/tags/rel_8/rtl/verilog
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7870d 18h /pci/tags/rel_8/rtl/verilog
73 Bug fixes, testcases added. mihad 7876d 18h /pci/tags/rel_8/rtl/verilog
72 *** empty log message *** mihad 7923d 22h /pci/tags/rel_8/rtl/verilog
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7931d 14h /pci/tags/rel_8/rtl/verilog
69 Changed BIST signal names etc.. mihad 7968d 21h /pci/tags/rel_8/rtl/verilog
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7972d 07h /pci/tags/rel_8/rtl/verilog
67 Changed BIST signals for RAMs. tadejm 7972d 11h /pci/tags/rel_8/rtl/verilog
66 Changed empty status generation in pciw_fifo_control.v mihad 7975d 22h /pci/tags/rel_8/rtl/verilog
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7978d 20h /pci/tags/rel_8/rtl/verilog
63 Added additional testcase and changed rst name in BIST to trst mihad 7979d 00h /pci/tags/rel_8/rtl/verilog
62 Added BIST signals for RAMs. mihad 7981d 17h /pci/tags/rel_8/rtl/verilog
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7989d 17h /pci/tags/rel_8/rtl/verilog
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7989d 18h /pci/tags/rel_8/rtl/verilog
58 Removed all logic from asynchronous reset network mihad 7994d 18h /pci/tags/rel_8/rtl/verilog
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7995d 00h /pci/tags/rel_8/rtl/verilog
56 Number of state bits define was removed mihad 7995d 15h /pci/tags/rel_8/rtl/verilog
55 Changed state machine encoding to true one-hot mihad 7995d 16h /pci/tags/rel_8/rtl/verilog
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8028d 21h /pci/tags/rel_8/rtl/verilog
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8029d 01h /pci/tags/rel_8/rtl/verilog
50 Got rid of undef directives mihad 8031d 17h /pci/tags/rel_8/rtl/verilog
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8031d 17h /pci/tags/rel_8/rtl/verilog
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8031d 18h /pci/tags/rel_8/rtl/verilog
47 Known issues repaired mihad 8031d 23h /pci/tags/rel_8/rtl/verilog
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8036d 18h /pci/tags/rel_8/rtl/verilog
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8037d 23h /pci/tags/rel_8/rtl/verilog
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8183d 03h /pci/tags/rel_8/rtl/verilog

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