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[/] [pci/] [tags/] [rel_8/] [rtl] - Rev 104

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Rev	Log message	Author	Age	Path
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7718d 14h	/pci/tags/rel_8/rtl
94	Changed one critical PCI bus signal logic.	mihad	7765d 12h	/pci/tags/rel_8/rtl
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7843d 09h	/pci/tags/rel_8/rtl
86	Entered the option to disable no response counter in wb master.	mihad	7855d 07h	/pci/tags/rel_8/rtl
83	Cleaned up the code. No functional changes.	mihad	7884d 04h	/pci/tags/rel_8/rtl
81	Updated synchronization in top level fifo modules.	mihad	7898d 00h	/pci/tags/rel_8/rtl
79	Updated.	mihad	7901d 05h	/pci/tags/rel_8/rtl
78	Old files with wrong names removed.	mihad	7901d 05h	/pci/tags/rel_8/rtl
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7901d 05h	/pci/tags/rel_8/rtl
73	Bug fixes, testcases added.	mihad	7907d 06h	/pci/tags/rel_8/rtl
72	* empty log message *	mihad	7954d 10h	/pci/tags/rel_8/rtl
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7962d 02h	/pci/tags/rel_8/rtl
69	Changed BIST signal names etc..	mihad	7999d 09h	/pci/tags/rel_8/rtl
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8002d 19h	/pci/tags/rel_8/rtl
67	Changed BIST signals for RAMs.	tadejm	8002d 23h	/pci/tags/rel_8/rtl
66	Changed empty status generation in pciw_fifo_control.v	mihad	8006d 10h	/pci/tags/rel_8/rtl
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8009d 08h	/pci/tags/rel_8/rtl
63	Added additional testcase and changed rst name in BIST to trst	mihad	8009d 12h	/pci/tags/rel_8/rtl
62	Added BIST signals for RAMs.	mihad	8012d 05h	/pci/tags/rel_8/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8020d 05h	/pci/tags/rel_8/rtl
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8020d 06h	/pci/tags/rel_8/rtl
58	Removed all logic from asynchronous reset network	mihad	8025d 06h	/pci/tags/rel_8/rtl
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8025d 12h	/pci/tags/rel_8/rtl
56	Number of state bits define was removed	mihad	8026d 03h	/pci/tags/rel_8/rtl
55	Changed state machine encoding to true one-hot	mihad	8026d 04h	/pci/tags/rel_8/rtl
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8059d 09h	/pci/tags/rel_8/rtl
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8059d 13h	/pci/tags/rel_8/rtl
50	Got rid of undef directives	mihad	8062d 05h	/pci/tags/rel_8/rtl
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8062d 05h	/pci/tags/rel_8/rtl
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8062d 05h	/pci/tags/rel_8/rtl

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[/] [pci/] [tags/] [rel_8/] [rtl] - Rev 104

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