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[/] [pci/] [tags/] [rel_8/] [rtl] - Rev 60

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Rev Log message Author Age Path
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7943d 14h /pci/tags/rel_8/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7943d 16h /pci/tags/rel_8/rtl
58 Removed all logic from asynchronous reset network mihad 7948d 16h /pci/tags/rel_8/rtl
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7948d 22h /pci/tags/rel_8/rtl
56 Number of state bits define was removed mihad 7949d 13h /pci/tags/rel_8/rtl
55 Changed state machine encoding to true one-hot mihad 7949d 13h /pci/tags/rel_8/rtl
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7982d 18h /pci/tags/rel_8/rtl
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7982d 23h /pci/tags/rel_8/rtl
50 Got rid of undef directives mihad 7985d 15h /pci/tags/rel_8/rtl
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7985d 15h /pci/tags/rel_8/rtl
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7985d 15h /pci/tags/rel_8/rtl
47 Known issues repaired mihad 7985d 21h /pci/tags/rel_8/rtl
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7990d 15h /pci/tags/rel_8/rtl
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7991d 21h /pci/tags/rel_8/rtl
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8137d 00h /pci/tags/rel_8/rtl
33 Added some testcases, removed un-needed fifo signals mihad 8152d 20h /pci/tags/rel_8/rtl
32 Added include statement that was missing and causing errors mihad 8160d 16h /pci/tags/rel_8/rtl
26 Modified testbench and fixed some bugs mihad 8166d 15h /pci/tags/rel_8/rtl
23 *** empty log message *** mihad 8184d 16h /pci/tags/rel_8/rtl
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8184d 16h /pci/tags/rel_8/rtl
19 *** empty log message *** mihad 8184d 17h /pci/tags/rel_8/rtl
18 *** empty log message *** mihad 8184d 17h /pci/tags/rel_8/rtl
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8303d 23h /pci/tags/rel_8/rtl
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8303d 23h /pci/tags/rel_8/rtl
2 New project directory structure mihad 8306d 16h /pci/tags/rel_8/rtl

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