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[/] [pci/] [tags/] [rel_8/] [rtl] - Rev 88

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Rev	Log message	Author	Age	Path
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7814d 04h	/pci/tags/rel_8/rtl
86	Entered the option to disable no response counter in wb master.	mihad	7826d 02h	/pci/tags/rel_8/rtl
83	Cleaned up the code. No functional changes.	mihad	7854d 23h	/pci/tags/rel_8/rtl
81	Updated synchronization in top level fifo modules.	mihad	7868d 19h	/pci/tags/rel_8/rtl
79	Updated.	mihad	7872d 00h	/pci/tags/rel_8/rtl
78	Old files with wrong names removed.	mihad	7872d 00h	/pci/tags/rel_8/rtl
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7872d 01h	/pci/tags/rel_8/rtl
73	Bug fixes, testcases added.	mihad	7878d 01h	/pci/tags/rel_8/rtl
72	* empty log message *	mihad	7925d 05h	/pci/tags/rel_8/rtl
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7932d 21h	/pci/tags/rel_8/rtl
69	Changed BIST signal names etc..	mihad	7970d 04h	/pci/tags/rel_8/rtl
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7973d 14h	/pci/tags/rel_8/rtl
67	Changed BIST signals for RAMs.	tadejm	7973d 18h	/pci/tags/rel_8/rtl
66	Changed empty status generation in pciw_fifo_control.v	mihad	7977d 05h	/pci/tags/rel_8/rtl
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7980d 03h	/pci/tags/rel_8/rtl
63	Added additional testcase and changed rst name in BIST to trst	mihad	7980d 07h	/pci/tags/rel_8/rtl
62	Added BIST signals for RAMs.	mihad	7983d 00h	/pci/tags/rel_8/rtl
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7991d 00h	/pci/tags/rel_8/rtl
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7991d 01h	/pci/tags/rel_8/rtl
58	Removed all logic from asynchronous reset network	mihad	7996d 01h	/pci/tags/rel_8/rtl
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7996d 07h	/pci/tags/rel_8/rtl
56	Number of state bits define was removed	mihad	7996d 22h	/pci/tags/rel_8/rtl
55	Changed state machine encoding to true one-hot	mihad	7996d 23h	/pci/tags/rel_8/rtl
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8030d 04h	/pci/tags/rel_8/rtl
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8030d 08h	/pci/tags/rel_8/rtl
50	Got rid of undef directives	mihad	8033d 00h	/pci/tags/rel_8/rtl
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8033d 00h	/pci/tags/rel_8/rtl
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8033d 01h	/pci/tags/rel_8/rtl
47	Known issues repaired	mihad	8033d 06h	/pci/tags/rel_8/rtl
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8038d 01h	/pci/tags/rel_8/rtl

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[/] [pci/] [tags/] [rel_8/] [rtl] - Rev 88

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