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[/] [pci/] [tags/] [rel_WB_B3/] [bench/] [verilog/] [system.v] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5598d 07h /pci/tags/rel_WB_B3/bench/verilog/system.v
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7625d 18h /pci/tags/rel_WB_B3/bench/verilog/system.v
119 Added support for WB B3. Some testcases were updated. tadejm 7625d 18h /pci/tags/rel_WB_B3/bench/verilog/system.v
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7643d 21h /pci/tags/rel_WB_B3/bench/verilog/system.v
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7649d 07h /pci/tags/rel_WB_B3/bench/verilog/system.v
92 Update! mihad 7696d 12h /pci/tags/rel_WB_B3/bench/verilog/system.v
87 Updated acording to RTL changes. mihad 7785d 23h /pci/tags/rel_WB_B3/bench/verilog/system.v
81 Updated synchronization in top level fifo modules. mihad 7828d 17h /pci/tags/rel_WB_B3/bench/verilog/system.v
73 Bug fixes, testcases added. mihad 7837d 23h /pci/tags/rel_WB_B3/bench/verilog/system.v
69 Changed BIST signal names etc.. mihad 7930d 02h /pci/tags/rel_WB_B3/bench/verilog/system.v
64 The testcase I just added in previous revision repaired mihad 7940d 03h /pci/tags/rel_WB_B3/bench/verilog/system.v
63 Added additional testcase and changed rst name in BIST to trst mihad 7940d 05h /pci/tags/rel_WB_B3/bench/verilog/system.v
62 Added BIST signals for RAMs. mihad 7942d 22h /pci/tags/rel_WB_B3/bench/verilog/system.v
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7956d 05h /pci/tags/rel_WB_B3/bench/verilog/system.v
52 Oops, never before noticed that OC header is missing mihad 7990d 06h /pci/tags/rel_WB_B3/bench/verilog/system.v
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7990d 06h /pci/tags/rel_WB_B3/bench/verilog/system.v
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7999d 04h /pci/tags/rel_WB_B3/bench/verilog/system.v
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8144d 07h /pci/tags/rel_WB_B3/bench/verilog/system.v
33 Added some testcases, removed un-needed fifo signals mihad 8160d 03h /pci/tags/rel_WB_B3/bench/verilog/system.v
26 Modified testbench and fixed some bugs mihad 8173d 22h /pci/tags/rel_WB_B3/bench/verilog/system.v
15 Initial testbench import. Still under development mihad 8192d 01h /pci/tags/rel_WB_B3/bench/verilog/system.v

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