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[/] [pci/] [tags/] [rel_WB_B3/] [rtl/] - Rev 106

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Rev Log message Author Age Path
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7716d 12h /pci/tags/rel_WB_B3/rtl
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7721d 22h /pci/tags/rel_WB_B3/rtl
94 Changed one critical PCI bus signal logic. mihad 7768d 20h /pci/tags/rel_WB_B3/rtl
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7846d 17h /pci/tags/rel_WB_B3/rtl
86 Entered the option to disable no response counter in wb master. mihad 7858d 14h /pci/tags/rel_WB_B3/rtl
83 Cleaned up the code. No functional changes. mihad 7887d 11h /pci/tags/rel_WB_B3/rtl
81 Updated synchronization in top level fifo modules. mihad 7901d 08h /pci/tags/rel_WB_B3/rtl
79 Updated. mihad 7904d 13h /pci/tags/rel_WB_B3/rtl
78 Old files with wrong names removed. mihad 7904d 13h /pci/tags/rel_WB_B3/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7904d 13h /pci/tags/rel_WB_B3/rtl
73 Bug fixes, testcases added. mihad 7910d 14h /pci/tags/rel_WB_B3/rtl
72 *** empty log message *** mihad 7957d 18h /pci/tags/rel_WB_B3/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7965d 09h /pci/tags/rel_WB_B3/rtl
69 Changed BIST signal names etc.. mihad 8002d 17h /pci/tags/rel_WB_B3/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8006d 02h /pci/tags/rel_WB_B3/rtl
67 Changed BIST signals for RAMs. tadejm 8006d 07h /pci/tags/rel_WB_B3/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 8009d 17h /pci/tags/rel_WB_B3/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8012d 16h /pci/tags/rel_WB_B3/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 8012d 20h /pci/tags/rel_WB_B3/rtl
62 Added BIST signals for RAMs. mihad 8015d 13h /pci/tags/rel_WB_B3/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8023d 12h /pci/tags/rel_WB_B3/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8023d 14h /pci/tags/rel_WB_B3/rtl
58 Removed all logic from asynchronous reset network mihad 8028d 14h /pci/tags/rel_WB_B3/rtl
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8028d 20h /pci/tags/rel_WB_B3/rtl
56 Number of state bits define was removed mihad 8029d 11h /pci/tags/rel_WB_B3/rtl
55 Changed state machine encoding to true one-hot mihad 8029d 11h /pci/tags/rel_WB_B3/rtl
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8062d 16h /pci/tags/rel_WB_B3/rtl
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8062d 21h /pci/tags/rel_WB_B3/rtl
50 Got rid of undef directives mihad 8065d 13h /pci/tags/rel_WB_B3/rtl
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8065d 13h /pci/tags/rel_WB_B3/rtl

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