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[/] [pci/] [tags/] [rel_WB_B3] - Rev 94

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Rev Log message Author Age Path
94 Changed one critical PCI bus signal logic. mihad 7701d 11h /pci/tags/rel_WB_B3
93 Added a test application! mihad 7701d 18h /pci/tags/rel_WB_B3
92 Update! mihad 7701d 18h /pci/tags/rel_WB_B3
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7737d 08h /pci/tags/rel_WB_B3
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7737d 08h /pci/tags/rel_WB_B3
89 Burst 2 error fixed. mihad 7773d 09h /pci/tags/rel_WB_B3
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7779d 08h /pci/tags/rel_WB_B3
87 Updated acording to RTL changes. mihad 7791d 05h /pci/tags/rel_WB_B3
86 Entered the option to disable no response counter in wb master. mihad 7791d 05h /pci/tags/rel_WB_B3
85 Changed Vendor ID defines. mihad 7791d 10h /pci/tags/rel_WB_B3
84 Changed vendor ID. mihad 7795d 04h /pci/tags/rel_WB_B3
83 Cleaned up the code. No functional changes. mihad 7820d 02h /pci/tags/rel_WB_B3
81 Updated synchronization in top level fifo modules. mihad 7833d 23h /pci/tags/rel_WB_B3
79 Updated. mihad 7837d 04h /pci/tags/rel_WB_B3
78 Old files with wrong names removed. mihad 7837d 04h /pci/tags/rel_WB_B3
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7837d 04h /pci/tags/rel_WB_B3
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7840d 04h /pci/tags/rel_WB_B3
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7843d 04h /pci/tags/rel_WB_B3
73 Bug fixes, testcases added. mihad 7843d 05h /pci/tags/rel_WB_B3
72 *** empty log message *** mihad 7890d 08h /pci/tags/rel_WB_B3
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7898d 00h /pci/tags/rel_WB_B3
69 Changed BIST signal names etc.. mihad 7935d 08h /pci/tags/rel_WB_B3
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7938d 17h /pci/tags/rel_WB_B3
67 Changed BIST signals for RAMs. tadejm 7938d 22h /pci/tags/rel_WB_B3
66 Changed empty status generation in pciw_fifo_control.v mihad 7942d 08h /pci/tags/rel_WB_B3
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7945d 07h /pci/tags/rel_WB_B3
64 The testcase I just added in previous revision repaired mihad 7945d 09h /pci/tags/rel_WB_B3
63 Added additional testcase and changed rst name in BIST to trst mihad 7945d 11h /pci/tags/rel_WB_B3
62 Added BIST signals for RAMs. mihad 7948d 04h /pci/tags/rel_WB_B3
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7956d 03h /pci/tags/rel_WB_B3

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