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[/] [potato/] - Rev 66

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66 Change UART status register to include recv buffer empty

This replaces bit 0 in the status register, previously used
for recv buffer _not_ empty, with a bit indicating if the
recv buffer _is_ empty.		 skordal 3178d 12h /potato
65 Update platform headers and add cache control commands

Cache control is currently no-ops on Potato.		 skordal 3244d 19h /potato
64 Add display enable support for the 7-seg module skordal 3244d 19h /potato
63 Upgrade makefiles for use with the upgraded toolchain skordal 3247d 19h /potato
62 Add a couple of missing signals to a sensitivity list skordal 3275d 20h /potato
61 Add 7-segment display controller to the Potato SoC skordal 3276d 23h /potato
60 Remove out-of-date comment skordal 3290d 15h /potato
59 Remove branch: "new-privileged-isa" skordal 3310d 17h /potato
58 Merge branch new-privileged-isa (r48-r57) into trunk

This adds support for the newly published supervisor extensions
version 1.7. In addition, a processor datasheet has been added
and the timer_clk signal has been properly connected in the
example design and the SoC testbench.		 skordal 3310d 19h /potato
57 Add processor datasheet skordal 3310d 20h /potato
56 Remove old and outdated processor manual skordal 3310d 20h /potato
55 Use timer_clk for the example design and SoC testbench skordal 3310d 22h /potato
54 Update benchmarks to work with supervisor spec v1.7 skordal 3315d 12h /potato
53 Upgrade processor core to conform to the supervisor spec v1.7 skordal 3317d 13h /potato
52 Correct .data section of sw-jal test skordal 3317d 13h /potato
51 Add scall/ecall, sbreak/ebreak and timer interrupt tests skordal 3317d 13h /potato
50 Update test environment to the new supervisor ISA skordal 3329d 13h /potato
49 Correct spelling of "privileged" skordal 3339d 12h /potato
48 Create branch for upgrading to the new privileged ISA skordal 3339d 13h /potato
47 Tag version 0.1 of the Potato Processor skordal 3339d 20h /potato
46 Remove branch: cache-playground skordal 3342d 14h /potato
45 Merge branch cache-playground (r23-r30 and r34-r44) into trunk

This primarily adds the following features the the processor:
- A direct-mapped instruction cache with configurable cache line width and
number of cache lines.
- Various bug fixes for bugs that appeared when the processor could run
instructions at full speed but had to stall for data.
- A "Hello World" test application.		 skordal 3342d 14h /potato
44 Add instruction cache and use the WB adapter as dmem interface skordal 3342d 15h /potato
43 Improve instruction fetch logic skordal 3342d 15h /potato
42 Move check for stall from irq_asserted to exception_taken in EX stage skordal 3342d 15h /potato
41 Make continouous status register reads asynchronous skordal 3342d 15h /potato
40 Reduce example design clock frequency to 50 MHz

- Also includes a minor change to make the address decoder/interconnect work
better with burst transfers.		 skordal 3342d 15h /potato
39 Disable IRQs when handling exceptions skordal 3342d 15h /potato
38 Add "Hello World" test application skordal 3342d 16h /potato
37 Add macro to set the TOHOST register from C code skordal 3342d 16h /potato

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