OpenCores
URL https://opencores.org/ocsvn/raptor64/raptor64/trunk

Subversion Repositories raptor64

[/] [raptor64/] [trunk/] [rtl/] [verilog] - Rev 52

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 - most recent updates to
- compiler (thread keyword) , shift bug fix
- CPU segmentation model update
- SimpleMMU added
robfinch 4192d 19h /raptor64/trunk/rtl/verilog
50 - interrupt work robfinch 4207d 00h /raptor64/trunk/rtl/verilog
48 - fixed pipeline bug
- added segment registers
- updated bootrom
robfinch 4211d 11h /raptor64/trunk/rtl/verilog
45 - separate exception status per context
- debugging PC
-
robfinch 4220d 02h /raptor64/trunk/rtl/verilog
44 - fix: assert byte select lines during burst access
- fixup bitfield instructions
robfinch 4226d 14h /raptor64/trunk/rtl/verilog
42 - updated assembler, sample files, 32 bit ISA robfinch 4230d 20h /raptor64/trunk/rtl/verilog
41 - change to 32 bit ISA robfinch 4230d 20h /raptor64/trunk/rtl/verilog
33 - updated cpu files robfinch 4249d 16h /raptor64/trunk/rtl/verilog
31 - added more smaller modules robfinch 4450d 06h /raptor64/trunk/rtl/verilog
30 - separated out Branch History, regfile, and TLB robfinch 4451d 18h /raptor64/trunk/rtl/verilog
29 - exception processing update robfinch 4454d 13h /raptor64/trunk/rtl/verilog
25 - updated processor robfinch 4464d 13h /raptor64/trunk/rtl/verilog
21 - fixes, loop, instruction buffer robfinch 4477d 10h /raptor64/trunk/rtl/verilog
20 - more source changes robfinch 4481d 15h /raptor64/trunk/rtl/verilog
19 - added instruction buffer for non-icache operation robfinch 4481d 15h /raptor64/trunk/rtl/verilog
16 - working on interrupt hardware robfinch 4482d 14h /raptor64/trunk/rtl/verilog
15 - disassembles opcodes for diagnostic dump robfinch 4483d 07h /raptor64/trunk/rtl/verilog
14 - many changes
- removed cmd bus from sc version
-
robfinch 4483d 07h /raptor64/trunk/rtl/verilog
13 - single context (sc) version of cpu robfinch 4485d 12h /raptor64/trunk/rtl/verilog
12 - updated for updated instruction set
- added WB ROM
robfinch 4485d 12h /raptor64/trunk/rtl/verilog
11 - fixes, changed branches around robfinch 4485d 12h /raptor64/trunk/rtl/verilog
9 - added (2,2) branch predictor
- added more instruction dumps
robfinch 4486d 18h /raptor64/trunk/rtl/verilog
7 - diagnostic instruction dump robfinch 4487d 12h /raptor64/trunk/rtl/verilog
6 - numerous fixes (work in progress) robfinch 4487d 12h /raptor64/trunk/rtl/verilog
5 - numerous fixes (work in progress) robfinch 4487d 12h /raptor64/trunk/rtl/verilog
4 - uneeded; text editor colors robfinch 4488d 01h /raptor64/trunk/rtl/verilog
3 uploading initial archive of Raptor64 robfinch 4488d 01h /raptor64/trunk/rtl/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.