OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp/] [memblock.vhd] - Rev 250

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4433d 21h /raytrac/branches/fp/memblock.vhd
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4438d 05h /raytrac/branches/fp/memblock.vhd
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4438d 12h /raytrac/branches/fp/memblock.vhd
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4440d 21h /raytrac/branches/fp/memblock.vhd
174 Comment tweaking... its the same RTL anyway jguarin2002 4477d 08h /raytrac/branches/fp/memblock.vhd
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4483d 12h /raytrac/branches/fp/memblock.vhd
160 Corrections derived from simulation debugging jguarin2002 4488d 04h /raytrac/branches/fp/memblock.vhd
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4489d 14h /raytrac/branches/fp/memblock.vhd
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4489d 18h /raytrac/branches/fp/memblock.vhd
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4490d 06h /raytrac/branches/fp/memblock.vhd
153 last modifications for tb_compiler.py compliance jguarin2002 4496d 10h /raytrac/branches/fp/memblock.vhd
152 Test bench oriented modifications jguarin2002 4500d 11h /raytrac/branches/fp/memblock.vhd
151 Previous Work to generate test benching jguarin2002 4559d 07h /raytrac/branches/fp/memblock.vhd
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4573d 04h /raytrac/branches/fp/memblock.vhd
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4575d 20h /raytrac/branches/fp/memblock.vhd
143 working on result queue sync decoding signals jguarin2002 4599d 23h /raytrac/branches/fp/memblock.vhd
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4671d 23h /raytrac/branches/fp/memblock.vhd
140 Syncing: its awful work..... jguarin2002 4672d 05h /raytrac/branches/fp/memblock.vhd
139 Sync jguarin2002 4683d 19h /raytrac/branches/fp/memblock.vhd
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4688d 11h /raytrac/branches/fp/memblock.vhd
136 gogogo jguarin2002 4696d 22h /raytrac/branches/fp/memblock.vhd
133 Added the instructions queue jguarin2002 4704d 10h /raytrac/branches/fp/memblock.vhd
131 Post RTL check on memblock jguarin2002 4708d 12h /raytrac/branches/fp/memblock.vhd
130 RayTrac Internal Memory Blocks among operands registers and Intermediate Results Fifos jguarin2002 4709d 06h /raytrac/branches/fp/memblock.vhd
129 Memory Block:

Identified the four circuits: External Write, External Read, Internal Write, Internal Read.		 jguarin2002 4714d 19h /raytrac/branches/fp/memblock.vhd
128 Memblock, for input registers and intermezzo results queues: normfifox26x96 & dpfifo9x64, dpc is done jguarin2002 4721d 22h /raytrac/branches/fp/memblock.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.