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[/] [raytrac/] [trunk/] [arithpack.vhd] - Rev 74

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74 On the rush, correct chip floor planning problem jguarin2002 4803d 23h /raytrac/trunk/arithpack.vhd
73 Almost Ready Division and Square Root jguarin2002 4805d 04h /raytrac/trunk/arithpack.vhd
60 Shifter circuit for Division Phase one done jguarin2002 4815d 09h /raytrac/trunk/arithpack.vhd
59 Tarde con pintiti, paquete aritmetico se anade raiz shifter y sqrt jguarin2002 4818d 15h /raytrac/trunk/arithpack.vhd
52 Working...... jguarin2002 4865d 01h /raytrac/trunk/arithpack.vhd
50 There's now a descent testbench\!\!\! jguarin2002 4873d 07h /raytrac/trunk/arithpack.vhd
49 Test bench ifs finally running jguarin2002 4874d 02h /raytrac/trunk/arithpack.vhd
47 Started making tests, but dont understand quite well the mechanics of Modelsim. Change Arithpack for quicker multiplier and memory instantiation jguarin2002 4877d 10h /raytrac/trunk/arithpack.vhd
45 Magic is already written... now we shall set the testbench on fire\! jguarin2002 4879d 00h /raytrac/trunk/arithpack.vhd
44 All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif... jguarin2002 4880d 01h /raytrac/trunk/arithpack.vhd
43 Nothing to say, just working on the Test Bench... jguarin2002 4880d 09h /raytrac/trunk/arithpack.vhd
42 no comment no tb yet: jguarin2002 4881d 03h /raytrac/trunk/arithpack.vhd
40 test bench changes..... jguarin2002 4883d 14h /raytrac/trunk/arithpack.vhd
32 carry_logic parameter added to uf entity jguarin2002 4893d 16h /raytrac/trunk/arithpack.vhd
27 Optimized code, using IEEE libraries and extra parameters to make a more legible code jguarin2002 4907d 23h /raytrac/trunk/arithpack.vhd
26 Corrections on opcoder jguarin2002 4908d 03h /raytrac/trunk/arithpack.vhd
25 Support to variable width and the possibility to choose between behavioral description and structural description jguarin2002 4908d 03h /raytrac/trunk/arithpack.vhd
24 Added a more simple mux to opcoder implementation. jguarin2002 4914d 20h /raytrac/trunk/arithpack.vhd
23 Doxygen documentation related changes..... jguarin2002 4914d 20h /raytrac/trunk/arithpack.vhd
22 Doxygen Documentation related changes. jguarin2002 4915d 12h /raytrac/trunk/arithpack.vhd
16 Commiting differences related to Doxygen documentation adding jguarin2002 4920d 01h /raytrac/trunk/arithpack.vhd
15 When selecting s0name, s1name, for a signal that belongs to a 2 stage pipe, the compiler would, based on the name, create just a single flipflop with Q feedbacking D, and that's no the case, so a lot of names has been changed, from s0signalname, s1signalname to stage0signalname, s1signalname and so on... jguarin2002 4922d 13h /raytrac/trunk/arithpack.vhd
14 Lots of typos fixed...... jguarin2002 4924d 13h /raytrac/trunk/arithpack.vhd
13 syntax typo fixed... jguarin2002 4924d 15h /raytrac/trunk/arithpack.vhd
12 syntax typo fixed... jguarin2002 4924d 15h /raytrac/trunk/arithpack.vhd
10 arithpack component declaration changed to make a more 'understandable' design, perhaps wont be that legible but at this stage, at least to me it is jguarin2002 4930d 06h /raytrac/trunk/arithpack.vhd
9 dumped fastmux, did not need it at all (by now), therefore arithpack.vhd was modified, by deleting the fastmux component declaration jguarin2002 4930d 09h /raytrac/trunk/arithpack.vhd
8 uf.vhd now is complete, got to assemble the whole uf.vhd and opcoder and the raytracing engine will be completed jguarin2002 4930d 14h /raytrac/trunk/arithpack.vhd
2 In next check in i will comment in a richer and significant way, for now Im on planning Stage ..... jguarin2002 4936d 01h /raytrac/trunk/arithpack.vhd

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