Rev |
Log message |
Author |
Age |
Path |
82 |
FPBRANCH releaseeeesvn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd svn add fpbranch/get.vhd fpbranch/sm.vhd fpbranch/slr.vhd fpbranch/mmp.vhd |
jguarin2002 |
4778d 02h |
/raytrac/trunk/fpbranch/arithpack.vhd |
81 |
Almost There |
jguarin2002 |
4782d 00h |
/arithpack.vhd |
77 |
Now support for addition and substraction of A(7,10) component vectors |
jguarin2002 |
4794d 12h |
/arithpack.vhd |
76 |
Upgrade para obtener una mantissa de 20 bits |
jguarin2002 |
4796d 10h |
/arithpack.vhd |
74 |
On the rush, correct chip floor planning problem |
jguarin2002 |
4802d 23h |
/arithpack.vhd |
73 |
Almost Ready Division and Square Root |
jguarin2002 |
4804d 04h |
/arithpack.vhd |
60 |
Shifter circuit for Division Phase one done |
jguarin2002 |
4814d 08h |
/arithpack.vhd |
59 |
Tarde con pintiti, paquete aritmetico se anade raiz shifter y sqrt |
jguarin2002 |
4817d 14h |
/arithpack.vhd |
52 |
Working...... |
jguarin2002 |
4864d 01h |
/arithpack.vhd |
50 |
There's now a descent testbench\!\!\! |
jguarin2002 |
4872d 07h |
/arithpack.vhd |
49 |
Test bench ifs finally running |
jguarin2002 |
4873d 01h |
/arithpack.vhd |
47 |
Started making tests, but dont understand quite well the mechanics of Modelsim. Change Arithpack for quicker multiplier and memory instantiation |
jguarin2002 |
4876d 10h |
/arithpack.vhd |
45 |
Magic is already written... now we shall set the testbench on fire\! |
jguarin2002 |
4878d 00h |
/arithpack.vhd |
44 |
All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif... |
jguarin2002 |
4879d 01h |
/arithpack.vhd |
43 |
Nothing to say, just working on the Test Bench... |
jguarin2002 |
4879d 09h |
/arithpack.vhd |
42 |
no comment no tb yet: |
jguarin2002 |
4880d 02h |
/arithpack.vhd |
40 |
test bench changes..... |
jguarin2002 |
4882d 14h |
/arithpack.vhd |
32 |
carry_logic parameter added to uf entity |
jguarin2002 |
4892d 16h |
/arithpack.vhd |
27 |
Optimized code, using IEEE libraries and extra parameters to make a more legible code |
jguarin2002 |
4906d 23h |
/arithpack.vhd |
26 |
Corrections on opcoder |
jguarin2002 |
4907d 03h |
/arithpack.vhd |
25 |
Support to variable width and the possibility to choose between behavioral description and structural description |
jguarin2002 |
4907d 03h |
/arithpack.vhd |
24 |
Added a more simple mux to opcoder implementation. |
jguarin2002 |
4913d 20h |
/arithpack.vhd |
23 |
Doxygen documentation related changes..... |
jguarin2002 |
4913d 20h |
/arithpack.vhd |
22 |
Doxygen Documentation related changes. |
jguarin2002 |
4914d 11h |
/arithpack.vhd |
16 |
Commiting differences related to Doxygen documentation adding |
jguarin2002 |
4919d 01h |
/arithpack.vhd |
15 |
When selecting s0name, s1name, for a signal that belongs to a 2 stage pipe, the compiler would, based on the name, create just a single flipflop with Q feedbacking D, and that's no the case, so a lot of names has been changed, from s0signalname, s1signalname to stage0signalname, s1signalname and so on... |
jguarin2002 |
4921d 13h |
/arithpack.vhd |
14 |
Lots of typos fixed...... |
jguarin2002 |
4923d 13h |
/arithpack.vhd |
13 |
syntax typo fixed... |
jguarin2002 |
4923d 14h |
/arithpack.vhd |
12 |
syntax typo fixed... |
jguarin2002 |
4923d 15h |
/arithpack.vhd |
10 |
arithpack component declaration changed to make a more 'understandable' design, perhaps wont be that legible but at this stage, at least to me it is |
jguarin2002 |
4929d 06h |
/arithpack.vhd |