OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac] - Rev 153

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
153 last modifications for tb_compiler.py compliance jguarin2002 4506d 20h /raytrac
152 Test bench oriented modifications jguarin2002 4510d 21h /raytrac
151 Previous Work to generate test benching jguarin2002 4569d 17h /raytrac
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4583d 14h /raytrac
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4583d 17h /raytrac
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4583d 18h /raytrac
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4586d 06h /raytrac
146 Interruption Machine jguarin2002 4594d 00h /raytrac
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4598d 13h /raytrac
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4605d 17h /raytrac
143 working on result queue sync decoding signals jguarin2002 4610d 09h /raytrac
142 Additions for the State Machine jguarin2002 4615d 08h /raytrac
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4682d 09h /raytrac
140 Syncing: its awful work..... jguarin2002 4682d 15h /raytrac
139 Sync jguarin2002 4694d 05h /raytrac
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4698d 20h /raytrac
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4704d 21h /raytrac
136 gogogo jguarin2002 4707d 08h /raytrac
135 Correction on conectiveness of Datapath Control... jguarin2002 4711d 09h /raytrac
134 State Machine, for addressing counting, internal writing & reading control and interruption generation jguarin2002 4713d 04h /raytrac
133 Added the instructions queue jguarin2002 4714d 20h /raytrac
132 There was amiss in the cross product datapath decoder jguarin2002 4718d 16h /raytrac
131 Post RTL check on memblock jguarin2002 4718d 22h /raytrac
130 RayTrac Internal Memory Blocks among operands registers and Intermediate Results Fifos jguarin2002 4719d 16h /raytrac
129 Memory Block:

Identified the four circuits: External Write, External Read, Internal Write, Internal Read.		 jguarin2002 4725d 05h /raytrac
128 Memblock, for input registers and intermezzo results queues: normfifox26x96 & dpfifo9x64, dpc is done jguarin2002 4732d 07h /raytrac
127 Datapath Control
Done		 jguarin2002 4732d 19h /raytrac
126 dpc: Datapath Control Finished..... test it jguarin2002 4736d 14h /raytrac
125 DPC the result is just left jguarin2002 4737d 08h /raytrac
124 lost.... jguarin2002 4741d 08h /raytrac

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.