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Rev Log message Author Age Path
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4541d 02h /raytrac
153 last modifications for tb_compiler.py compliance jguarin2002 4541d 02h /raytrac
152 Test bench oriented modifications jguarin2002 4545d 03h /raytrac
151 Previous Work to generate test benching jguarin2002 4603d 23h /raytrac
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4617d 20h /raytrac
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4617d 23h /raytrac
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4617d 23h /raytrac
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4620d 12h /raytrac
146 Interruption Machine jguarin2002 4628d 05h /raytrac
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4632d 19h /raytrac
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4639d 23h /raytrac
143 working on result queue sync decoding signals jguarin2002 4644d 15h /raytrac
142 Additions for the State Machine jguarin2002 4649d 13h /raytrac
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4716d 15h /raytrac
140 Syncing: its awful work..... jguarin2002 4716d 21h /raytrac
139 Sync jguarin2002 4728d 11h /raytrac
138 enabled ena on memblock and dpc, also changed the instruction and result memories to queued schemes jguarin2002 4733d 02h /raytrac
137 Syncing with enables and eleminated all the register outputs since none block should carry on a register output jguarin2002 4739d 03h /raytrac
136 gogogo jguarin2002 4741d 14h /raytrac
135 Correction on conectiveness of Datapath Control... jguarin2002 4745d 14h /raytrac
134 State Machine, for addressing counting, internal writing & reading control and interruption generation jguarin2002 4747d 10h /raytrac
133 Added the instructions queue jguarin2002 4749d 02h /raytrac
132 There was amiss in the cross product datapath decoder jguarin2002 4752d 21h /raytrac
131 Post RTL check on memblock jguarin2002 4753d 03h /raytrac
130 RayTrac Internal Memory Blocks among operands registers and Intermediate Results Fifos jguarin2002 4753d 22h /raytrac
129 Memory Block:

Identified the four circuits: External Write, External Read, Internal Write, Internal Read.
jguarin2002 4759d 11h /raytrac
128 Memblock, for input registers and intermezzo results queues: normfifox26x96 & dpfifo9x64, dpc is done jguarin2002 4766d 13h /raytrac
127 Datapath Control
Done
jguarin2002 4767d 01h /raytrac
126 dpc: Datapath Control Finished..... test it jguarin2002 4770d 20h /raytrac
125 DPC the result is just left jguarin2002 4771d 14h /raytrac

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