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169 Long Stupid, version of a 32 bit floating point I3E754 Adder jguarin2002 4458d 11h /raytrac
168 Added a display function for vectorblock02 jguarin2002 4461d 01h /raytrac
167 Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync jguarin2002 4461d 01h /raytrac
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4461d 11h /raytrac
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4461d 20h /raytrac
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4462d 21h /raytrac
163 dpc: Signals to eval in functional simulatio. Fix on the codification of the sign applied into the arithmetic block depending on the UCA code of the instruction being excuted. Also a correction was done on the decodification of the result queues write signals. A correction applied on the decodification of the interruptions generated due to full queues. RayTrac: A signal to decode the sign that goes into the addition operations was made as long with its combinatorial operation to calculate it. Fadd32: Signals to eval in functional simulation. An important bug was fixed when decoding the shift to normalize the mantissa of the float number with the minor exponent, that was causing a misscalculation of the normalized mantissa. Arithpack: Formatting of the instruction at function ap_format_instruction fixed due to a change in the opcodes of the unary instructions. jguarin2002 4462d 23h /raytrac
162 Señales para evaluar en simulación funcional jguarin2002 4463d 00h /raytrac
161 Changes for the sake of the firsts simulation tracking results jguarin2002 4464d 15h /raytrac
160 Corrections derived from simulation debugging jguarin2002 4469d 07h /raytrac
159 wrcycle\!\? No\! rwcycle.... jguarin2002 4470d 17h /raytrac
158 Changing std_logic_vector types to my custom far more convinients xfloat32\! jguarin2002 4470d 21h /raytrac
157 For the first time the whole Raytrac RTL code compiled along with its testbench code in ModelSim jguarin2002 4471d 09h /raytrac
156 Test Bench Beta 0.1 jguarin2002 4471d 21h /raytrac
155 Changes applied prior to testbenching using the script tb_compiler.py jguarin2002 4474d 21h /raytrac
154 rt_tb.vhd: This file will be used as the test bench main file jguarin2002 4477d 13h /raytrac
153 last modifications for tb_compiler.py compliance jguarin2002 4477d 13h /raytrac
152 Test bench oriented modifications jguarin2002 4481d 14h /raytrac
151 Previous Work to generate test benching jguarin2002 4540d 10h /raytrac
150 First Beta of RayTrac for a total size of 3874 lcells. Great Result\! jguarin2002 4554d 07h /raytrac
149 Results Queue writing signals set on a single standard logic vector rather than in individual bits jguarin2002 4554d 11h /raytrac
148 Added an extra stage for the C.D DataPath so it takes the same ammount of clocks to calculate as A.B jguarin2002 4554d 11h /raytrac
147 Added Interruption Machine, supporting Result Queue Full and End Of Instruction event notifications. Memblock Adjustments. In the Data Path Control circuit an Interrupt pero Instruction type was decodified. jguarin2002 4556d 23h /raytrac
146 Interruption Machine jguarin2002 4564d 17h /raytrac
145 State machine and counters finishedifconfigifconfigifconfig! Now gather components to obtain RAYTRACifconfigifconfig jguarin2002 4569d 07h /raytrac
144 The commented part of DPC was erased, and no longer needed. jguarin2002 4576d 10h /raytrac
143 working on result queue sync decoding signals jguarin2002 4581d 03h /raytrac
142 Additions for the State Machine jguarin2002 4586d 01h /raytrac
141 Syncing: its awful work: input adresses decoded to include the instructions queue also.... jguarin2002 4653d 02h /raytrac
140 Syncing: its awful work..... jguarin2002 4653d 08h /raytrac

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