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[/] [raytrac] - Rev 193

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Rev Log message Author Age Path
193 WIP: Main Document jguarin2002 4477d 13h /raytrac
192 Some change I dont realize what is it in the design document (xls) jguarin2002 4478d 00h /raytrac
191 Reduced the implementation of Instruction Queue to 16 instructions rather than 32 and using registers in logic cells rather than M9Ks memory blocks.... finally the design fits. jguarin2002 4478d 00h /raytrac
190 M9K Block reduction. And Altera Compiler Directive was added to adder code to prevent unnecesary M9K block inferring... jguarin2002 4482d 09h /raytrac
189 Limiting Block size on the operands register to a maximum of 256 jguarin2002 4482d 15h /raytrac
188 Fitting Report jguarin2002 4483d 22h /raytrac
187 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4483d 22h /raytrac
186 Sopc claims that int is a name that conflicts with verilog or vhdl standards, so a change on the int port was made by renaming it to irq jguarin2002 4483d 22h /raytrac
185 Well mulblock was a void inside file.... jguarin2002 4484d 12h /raytrac
184 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4484d 16h /raytrac
183 Se quitó la palabra capítulo de los titulos de los capítulos. jguarin2002 4484d 16h /raytrac
182 Sobre la sincronización del RayTrac al escribir instrucciones y operandos. Pagina 29 y 31. jguarin2002 4484d 17h /raytrac
181 Version beta 0.2 previo a conexion con bus avalon en QSYS/SOPC jguarin2002 4485d 00h /raytrac
180 Documentos de diseño y documento final jguarin2002 4485d 00h /raytrac
179 light change on code readbility for Datapath Control hardware description hdl file jguarin2002 4485d 21h /raytrac
178 QSYS SOPC Raytrac component.... jguarin2002 4509d 12h /raytrac
177 Interruptions separated in diferent output ports, so we can assign them as interruptions senders.... each one of them..... jguarin2002 4509d 12h /raytrac
176 Little changes on full result queue signals codification in order to fix a potential bug that havent beed detected at the time of the change in the code jguarin2002 4521d 10h /raytrac
175 Fixed a problem on the writing signal of results queue 5,6 and 7. The error was detected just right when a calculated normalized vector was about to be written in the results queues 5 6 and 7 and the write signals of those were not activated (it would remain in 0), after checking what was the problem, a codification bug was spotted. jguarin2002 4521d 11h /raytrac
174 Comment tweaking... its the same RTL anyway jguarin2002 4521d 11h /raytrac
173 Added a procedure to support vectorblock03 type variables rendering after testbench execution jguarin2002 4521d 11h /raytrac
172 Results fifo writing signals added to the testbench jguarin2002 4521d 11h /raytrac
171 After some raytrac simulation result analysis, some bugs were detected on the decodification of several datapaths. Corrections were done and tested jguarin2002 4521d 11h /raytrac
170 Slim, suited to fit, elegant and small, optimized and well designed single precision floating point I3E754 32 bit adder jguarin2002 4521d 11h /raytrac
169 Long Stupid, version of a 32 bit floating point I3E754 Adder jguarin2002 4521d 11h /raytrac
168 Added a display function for vectorblock02 jguarin2002 4524d 01h /raytrac
167 Corrections on the moment the dot product and normalization queues are "rd_ack\'ed", they were a cycle earlier than they should causing pipeline desync jguarin2002 4524d 01h /raytrac
166 A strong revision on the decodification of the places to shift must be done..... I mean s5factor is EATING memory (Altera Synthesis), perhaps thats a better way jguarin2002 4524d 11h /raytrac
165 Fix on the decodification of factor to add or sub to the final exponent after mantissa normalization (Stage 5, s5factor) jguarin2002 4524d 20h /raytrac
164 reverting the not(s0delta(7)) change on revision 163 to s0delta(7) again jguarin2002 4525d 21h /raytrac

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