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[/] [sdhc-sc-core/] [trunk/] - Rev 188

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Rev Log message Author Age Path
188 Declared all targets phony to force building. rkastl 4961d 05h /sdhc-sc-core/trunk
187 Unit makefiles modified to reflect new location of Makefile.rules. rkastl 4961d 05h /sdhc-sc-core/trunk
186 Makefile adapted to new paths. rkastl 4961d 05h /sdhc-sc-core/trunk
185 Restructuring as source repository: Moved sources out of src subdirectory. rkastl 4961d 05h /sdhc-sc-core/trunk
184 Removed WbSlave shell (refs #69)
Moved verification sources to grpSdVerification (fixes #70)		 rkastl 4963d 23h /sdhc-sc-core/trunk
183 Removed unneeded wrapper (refs #69)
Sector count increased in TestWbMaster (refs #78)		 rkastl 4963d 23h /sdhc-sc-core/trunk
182 Fixes #60.

Synchronization logic moved to its own unit.		 rkastl 4963d 23h /sdhc-sc-core/trunk
181 Refs #60.

Fix synthesis with seperate WbClkDomain.		 rkastl 4963d 23h /sdhc-sc-core/trunk
180 Moved WbClkDomain to its own unit.
Refs #60.		 rkastl 4963d 23h /sdhc-sc-core/trunk
179 Fixing build:
Added library generation to Makefile.		 rkastl 4963d 23h /sdhc-sc-core/trunk
178 Fixed regression:
Testbenches did not support synchronous reset.		 rkastl 4963d 23h /sdhc-sc-core/trunk
177 Split SdTop into SdClkDomain and SdTop. Refs #60. rkastl 4963d 23h /sdhc-sc-core/trunk
176 Thesis:
Conclusion

Fixes #53,#61.		 rkastl 4963d 23h /sdhc-sc-core/trunk
175 Thesis:

Fixes #45.		 rkastl 4963d 23h /sdhc-sc-core/trunk
174 Thesis:
System integration

Fixes #51.		 rkastl 4963d 23h /sdhc-sc-core/trunk
173 Thesis:
Started with SdController description.

Refs #38.		 rkastl 4963d 23h /sdhc-sc-core/trunk
172 Thesis:
wbclockdomain: refactored and finished.

Fixes #39.		 rkastl 4963d 23h /sdhc-sc-core/trunk
171 Worked on wishbone part of thesis.

Refs #37.
Refs #39.		 rkastl 4963d 23h /sdhc-sc-core/trunk
170 License rewritten to BSD rkastl 4963d 23h /sdhc-sc-core/trunk
169 +sdc file for timing analysis rkastl 4963d 23h /sdhc-sc-core/trunk
168 TbdSd synthesis script reaches timing constraints. rkastl 4963d 23h /sdhc-sc-core/trunk
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4963d 23h /sdhc-sc-core/trunk
166 tbTbdSd: fixed rkastl 4963d 23h /sdhc-sc-core/trunk
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4963d 23h /sdhc-sc-core/trunk
164 Headers updated (LGPL, consistent format) rkastl 4963d 23h /sdhc-sc-core/trunk
163 Header-Skript supports writing to file and infile replacement. rkastl 4963d 23h /sdhc-sc-core/trunk
162 Script for generating headers created. rkastl 4963d 23h /sdhc-sc-core/trunk
161 Verification:
CardModel: Check CRC on received data		 rkastl 4963d 23h /sdhc-sc-core/trunk
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4963d 23h /sdhc-sc-core/trunk
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4963d 23h /sdhc-sc-core/trunk

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