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[/] [sdhc-sc-core/] [trunk/] [src/] - Rev 167

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Rev	Log message	Author	Age	Path
167	Read+Modify+Write works on HW + Fixed CRC status token (not mentioned in simplified spec) + Improved TestWbMaster to RMW	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
166	tbTbdSd: fixed	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
165	Only use synchronous high active reset in SDHC-SC-Core.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
164	Headers updated (LGPL, consistent format)	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
161	Verification: CardModel: Check CRC on received data	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
160	Verification: Full random read and write single blocks sequence works with checks. Checking the CRC in the card model is missing. Writing at addresses above the card size is missing. Erasing is missing.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
159	Verification: Further work: Checking RAM Actions and reading data is still missing	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
158	Verification: Work on Checking Functional coverage	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
157	Verification: Testcase with Reads works but Verification not completly implemented.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
156	SdVerification: + Split a SdCoreTransaction into multiple WbTransactions: Proof of Concept with a ReadSingleBlock-Transaction + Finish after certain amount of time and present simulation result	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
155	SdVerification: continue to work on it, not done.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
154	SdVerification: - started sending with mailboxes	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
153	SdVerification: further development, not done by far	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
152	SdClockMaster: Generate InStrobe so that it the sd bus gets captured on the rising edge of the clock in high speed mode	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
151	Verification: + redesign: not functional yet	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
150	Testbed: + Simulation made possible + Write works - Sometimes the alignment in the block is not right	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
149	SdBFM: + mailbox mode	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
148	SdVerification: + CardModel: Execution thread which starts initialization and then receives token and parses them. TbdSd: + Added SdWbSdSynchronization.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
147	Sd-Core: + Added checking of Busy signal after write	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
146	SdClockMaster: + fixed output of data at negedge of sclk in high speed mode	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
145	Verification: + SdCardModel and SdBFM seperated	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
140	Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete verification tb anyway.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
139	Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in the complete verification environment anyway.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
138	Removed testbench for unitSdCmd because it was a weak testbench and the functionality is tested in the SdVerificationTestbench anyway.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
137	Regression test suite: Removed unneeded testbenches from the makefile. Only complete reusable blocks are tested from now on.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
136	SDHC: - SdData refactored to use a single counter - TestWbMaster added to TbdSd (not functional yet)	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
134	SdData: Further refactoring.	rkastl	4931d 02h	/sdhc-sc-core/trunk/src
133	SdData: Further refactoring	rkastl	4931d 02h	/sdhc-sc-core/trunk/src

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[/] [sdhc-sc-core/] [trunk/] [src/] - Rev 167

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