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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitTbdSd] - Rev 185

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Rev	Log message	Author	Age	Path
185	Restructuring as source repository: Moved sources out of src subdirectory.	rkastl	5034d 05h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
184	Removed WbSlave shell (refs #69) Moved verification sources to grpSdVerification (fixes #70)	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
182	Fixes #60. Synchronization logic moved to its own unit.	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
181	Refs #60. Fix synthesis with seperate WbClkDomain.	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
178	Fixed regression: Testbenches did not support synchronous reset.	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
170	License rewritten to BSD	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
169	+sdc file for timing analysis	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
168	TbdSd synthesis script reaches timing constraints.	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
167	Read+Modify+Write works on HW + Fixed CRC status token (not mentioned in simplified spec) + Improved TestWbMaster to RMW	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
166	tbTbdSd: fixed	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
165	Only use synchronous high active reset in SDHC-SC-Core.	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
164	Headers updated (LGPL, consistent format)	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
151	Verification: + redesign: not functional yet	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
150	Testbed: + Simulation made possible + Write works - Sometimes the alignment in the block is not right	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
148	SdVerification: + CardModel: Execution thread which starts initialization and then receives token and parses them. TbdSd: + Added SdWbSdSynchronization.	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
144	Simulation files for tbTbdSd created. tbTbdSd is not done and TestWbMaster seems to be lost.	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
136	SDHC: - SdData refactored to use a single counter - TestWbMaster added to TbdSd (not functional yet)	rkastl	5036d 23h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	5037d 00h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
122	SdController: Initial read support	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
121	SdWbSlave inserted into SdTop. SdController does not use it yet.	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
113	Read with single block works on cards, but not in simulation. SdData.sv sends data with one "XXXX" cycle right before the crc.	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
111	Sclk moved to neg. edge -> setup and hold times for fast mode are easier to reach. (only micro sd does not work in fast mode).	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
110	All except microsd work in highspeed mode.	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
109	Added a data ram.	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
108	Added a ram to the testbed	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
106	Fixes #29: All cards respond, but they do not all work.	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
105	Changing speed works! refs #33	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
101	Receiving response to ACMD51 works including data, refs #33.	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
96	SdController: Region extracted from main state, select card in config state	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
94	CmdTimeout (8 Clocks) added, SdData inserted into top, refs #31	rkastl	5037d 03h	/sdhc-sc-core/trunk/src/grpSd/unitTbdSd

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[/] [sdhc-sc-core/] [trunk/] [src/] [grpSd/] [unitTbdSd] - Rev 185

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