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[/] [sdr_ctrl/] [trunk/] [verif] - Rev 68

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Rev Log message Author Age Path
68 SDRAM Address bit increased from 12 bit to 13 bit dinesha 4048d 01h /sdr_ctrl/trunk/verif
65 Updated Log file with CAS latency support 4,5 dinesha 4366d 08h /sdr_ctrl/trunk/verif
56 FPGA Synth optimisation dinesha 4486d 00h /sdr_ctrl/trunk/verif
53 Test bench upgradation dinesha 4489d 22h /sdr_ctrl/trunk/verif
49 clean up dinesha 4493d 01h /sdr_ctrl/trunk/verif
48 top-level cleanup dinesha 4493d 01h /sdr_ctrl/trunk/verif
46 test bench upgrade + rtl cleanup dinesha 4495d 02h /sdr_ctrl/trunk/verif
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4495d 06h /sdr_ctrl/trunk/verif
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4497d 04h /sdr_ctrl/trunk/verif
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4497d 06h /sdr_ctrl/trunk/verif
39 Test Bench upgradation with bigger data burst size dinesha 4498d 01h /sdr_ctrl/trunk/verif
38 Port Name clean up dinesha 4499d 06h /sdr_ctrl/trunk/verif
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4499d 08h /sdr_ctrl/trunk/verif
33 clean up dinesha 4500d 01h /sdr_ctrl/trunk/verif
32 Debug is enable through +define dinesha 4502d 00h /sdr_ctrl/trunk/verif
30 test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN dinesha 4502d 00h /sdr_ctrl/trunk/verif
29 SDRAM top and core related run file list are added into svn dinesha 4502d 00h /sdr_ctrl/trunk/verif
28 SDRAM top and SDRAM Core Golden files are added into SVN dinesha 4502d 00h /sdr_ctrl/trunk/verif
27 Golden log file corresponds the SDRAM core level test case are added into svn dinesha 4502d 22h /sdr_ctrl/trunk/verif
26 invalid log files are removed dinesha 4502d 22h /sdr_ctrl/trunk/verif
25 tb.sv is renamed as tb_top dinesha 4502d 22h /sdr_ctrl/trunk/verif
24 Clean Up dinesha 4502d 22h /sdr_ctrl/trunk/verif
22 Pad sdram clock added dinesha 4504d 04h /sdr_ctrl/trunk/verif
21 Clean up dinesha 4504d 04h /sdr_ctrl/trunk/verif
20 8 Bit SDARM support is added dinesha 4505d 22h /sdr_ctrl/trunk/verif
19 8 Bit SDRAM Support added dinesha 4505d 23h /sdr_ctrl/trunk/verif
18 8 Bit SDRAM Support is added dinesha 4505d 23h /sdr_ctrl/trunk/verif
17 micron 8 bit memory models are added into svn dinesha 4505d 23h /sdr_ctrl/trunk/verif
14 Unnecessary device config are removed dinesha 4509d 00h /sdr_ctrl/trunk/verif
12 Column Bits are made programmable dinesha 4509d 00h /sdr_ctrl/trunk/verif

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