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[/] [sdr_ctrl] - Rev 66

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Rev Log message Author Age Path
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4373d 23h /sdr_ctrl
65 Updated Log file with CAS latency support 4,5 dinesha 4374d 07h /sdr_ctrl
64 CAS Latency support added for 4,5 dinesha 4374d 07h /sdr_ctrl
63 FPGA Bench mark results are added dinesha 4493d 06h /sdr_ctrl
62 Synthesis constraint for simplify dinesha 4493d 06h /sdr_ctrl
61 RTL file list are added into SVN dinesha 4493d 07h /sdr_ctrl
60 warning cleanup dinesha 4493d 07h /sdr_ctrl
59 Control path request and data are register now for better FPGA timing dinesha 4493d 07h /sdr_ctrl
58 Read Data is register on RD_FAST=0 case dinesha 4493d 07h /sdr_ctrl
57 Synthesis constraints are added dinesha 4493d 21h /sdr_ctrl
56 FPGA Synth optimisation dinesha 4493d 23h /sdr_ctrl
55 FPGA Synthesis timing optimisation dinesha 4493d 23h /sdr_ctrl
54 FPGA Timing Optimisation dinesha 4496d 21h /sdr_ctrl
53 Test bench upgradation dinesha 4497d 21h /sdr_ctrl
52 Documentation update for request control and transfer control block dinesha 4497d 21h /sdr_ctrl
51 FPGA relating timing optimisation done dinesha 4497d 21h /sdr_ctrl
50 Bug fix the request length is fixe dinesha 4500d 01h /sdr_ctrl
49 clean up dinesha 4501d 00h /sdr_ctrl
48 top-level cleanup dinesha 4501d 00h /sdr_ctrl
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4501d 00h /sdr_ctrl
46 test bench upgrade + rtl cleanup dinesha 4503d 01h /sdr_ctrl
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4503d 05h /sdr_ctrl
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4505d 03h /sdr_ctrl
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4505d 05h /sdr_ctrl
42 Bug fix in read access is fixed dinesha 4505d 05h /sdr_ctrl
41 Updated Spec ver 0.1 is added back to svn dinesha 4505d 07h /sdr_ctrl
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4506d 00h /sdr_ctrl
39 Test Bench upgradation with bigger data burst size dinesha 4506d 00h /sdr_ctrl
38 Port Name clean up dinesha 4507d 05h /sdr_ctrl
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4507d 07h /sdr_ctrl

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