URL https://opencores.org/ocsvn/simpcon/simpcon/trunk

Subversion Repositories simpcon

[/] [simpcon/] [trunk] - Rev 30

Rev	Log message	Author	Age	Path
30	Update to V1.1	martin	5555d 01h	/simpcon/trunk
29	New and changed VHDL example files	martin	5555d 02h	/simpcon/trunk
26	New directory structure.	root	5638d 10h	/simpcon/trunk
25	clearification of simple read timing	martin	6121d 00h	/trunk
24	remived JOP library references	martin	6175d 00h	/trunk
23	no message	martin	6177d 03h	/trunk
22	update with Austrochip paper content and VHDL file descriptions	martin	6181d 16h	/trunk
21	VHDL update	martin	6181d 16h	/trunk
20	VHDL update	martin	6181d 19h	/trunk
19	moved to JOP handbook	martin	6181d 19h	/trunk
18	update from JOP	martin	6354d 18h	/trunk
17	SimpCon - Wishbone bridge	martin	6805d 01h	/trunk
16	Minimum SimpCon IO example	martin	6805d 01h	/trunk
15	ISA bus example (used to connect the CS8900 Ethernet chip)	martin	6805d 01h	/trunk
14	renamed to scio_min.vhd	martin	6805d 02h	/trunk
13	no message	martin	6814d 06h	/trunk
12	more IO examples	martin	6828d 05h	/trunk
11	no message	martin	6828d 05h	/trunk
10	Removed Flash ports	martin	6832d 21h	/trunk
9	Generic decoding and data mux	martin	6834d 07h	/trunk
8	Test IO slave and simple IO top	martin	6834d 09h	/trunk
7	Changed signal names to use the names from the specification.	martin	6836d 01h	/trunk
6	Signal section added	martin	6836d 04h	/trunk
5	Add document sources to the project	martin	6836d 04h	/trunk
4	A 32-bis static RAM slave with read pipeline level 2	martin	6836d 11h	/trunk
2	no message	martin	6836d 11h	/trunk
1	Standard project directories initialized by cvs2svn.		6836d 11h	/trunk