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[/] [simple_fm_receiver/] [trunk] - Rev 32

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Rev Log message Author Age Path
32 New directory structure. root 5564d 07h /simple_fm_receiver/trunk
31 Include flattening process, simplify build system. arif_endro 5776d 07h /trunk
30 Clean up. arif_endro 5820d 12h /trunk
29 Done fixing Makefile for Alliance. arif_endro 5820d 12h /trunk
28 chip IO place. arif_endro 5821d 08h /trunk
27 chip IO interface. arif_endro 5821d 08h /trunk
26 Removed. arif_endro 5821d 08h /trunk
25 IO place. arif_endro 5821d 08h /trunk
24 Update to use Alliance CAD System by ASIM/LIP6/UMPC arif_endro 5821d 10h /trunk
23 Disable clear signal. arif_endro 5821d 10h /trunk
22 Update last bit output assignment method. arif_endro 5821d 10h /trunk
20 New Version arif_endro 7006d 11h /trunk
19 Screen shot from chipscope analyzer view, this is how this design work. arif_endro 7012d 10h /trunk
18 This bit files generates better wave than previous (i.e. more smooth) arif_endro 7012d 12h /trunk
17 Initial Checkin arif_endro 7020d 09h /trunk
16 Changes constan and minor fix arif_endro 7023d 12h /trunk
15 Xilinx FPGA XC2V2000 bit files the first version. arif_endro 7026d 10h /trunk
14 *** empty log message *** arif_endro 7031d 08h /trunk
13 Update License arif_endro 7042d 09h /trunk
12 Update License
Change reset signal handle		 arif_endro 7042d 10h /trunk
11 Update License
Change reset signal handle		 arif_endro 7042d 10h /trunk
10 Added script for generating cos ROM. arif_endro 7052d 12h /trunk
9 Added documentation arif_endro 7069d 11h /trunk
7 To view chipscope exported output using ModelSim waveform window arif_endro 7083d 12h /trunk
6 Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO) arif_endro 7084d 14h /trunk
5 Added interface in/out and testing paralelly (e.g. square and triangular) arif_endro 7084d 14h /trunk
4 Fix elsif and if statement arif_endro 7087d 07h /trunk
2 Initial releases arif_endro 7090d 14h /trunk
1 Standard project directories initialized by cvs2svn. 7090d 14h /trunk

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