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[/] [socgen/] [trunk/] [Makefile] - Rev 113

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Rev Log message Author Age Path
113 started refactoring or1200 jt_eaton 4501d 19h /socgen/trunk/Makefile
112 added more test sims
removed unneeded files		 jt_eaton 4511d 08h /socgen/trunk/Makefile
106 checked in orp_soc project step 2 jt_eaton 4535d 02h /socgen/trunk/Makefile
103 added user guide
resynced to local repository		 jt_eaton 4559d 23h /socgen/trunk/Makefile
102 all ip-xact files now readable by kactus2 jt_eaton 4621d 19h /socgen/trunk/Makefile
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4622d 21h /socgen/trunk/Makefile
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4635d 04h /socgen/trunk/Makefile
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4677d 21h /socgen/trunk/Makefile
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4714d 02h /socgen/trunk/Makefile
96 hierConnections now create ports jt_eaton 4787d 22h /socgen/trunk/Makefile
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4823d 21h /socgen/trunk/Makefile
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4849d 21h /socgen/trunk/Makefile
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 4947d 04h /socgen/trunk/Makefile
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 4961d 22h /socgen/trunk/Makefile
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5030d 03h /socgen/trunk/Makefile
57 Now generate all filelists from xml files jt_eaton 5062d 23h /socgen/trunk/Makefile
56 soc_builder now builds verilog from xml files jt_eaton 5068d 08h /socgen/trunk/Makefile
54 now set up fpga targets from xml files jt_eaton 5071d 05h /socgen/trunk/Makefile
53 fixed check_fpgas jt_eaton 5073d 19h /socgen/trunk/Makefile
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5073d 23h /socgen/trunk/Makefile
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5110d 08h /socgen/trunk/Makefile
28 added T6502 processor
added vga_char_ctrl		 jt_eaton 5176d 07h /socgen/trunk/Makefile
20 added Nexys2 support
expanded docs
created tools directory		 jt_eaton 5208d 19h /socgen/trunk/Makefile
19 added serial_xmit module
updated and added docs		 jt_eaton 5216d 01h /socgen/trunk/Makefile
16 added geda scripts and symbols/sch jt_eaton 5223d 01h /socgen/trunk/Makefile
10 added impact_bat to generate svf files jt_eaton 5253d 06h /socgen/trunk/Makefile
6 added pic_micro from minirisc project with design to run code
on a digilent Basys board		 jt_eaton 5262d 02h /socgen/trunk/Makefile

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