URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [Makefile] - Rev 134

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Rev	Log message	Author	Age	Path
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3313d 07h	/socgen/trunk/Makefile
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3356d 08h	/socgen/trunk/Makefile
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3388d 05h	/socgen/trunk/Makefile
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3491d 22h	/socgen/trunk/Makefile
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3947d 04h	/socgen/trunk/Makefile
127	final cleanup before DAC	jt_eaton	4062d 01h	/socgen/trunk/Makefile
126	added mor1kx cleanup	jt_eaton	4115d 05h	/socgen/trunk/Makefile
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4159d 23h	/socgen/trunk/Makefile
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4256d 04h	/socgen/trunk/Makefile
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4308d 22h	/socgen/trunk/Makefile
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4344d 08h	/socgen/trunk/Makefile
117	added yellow pages tools	jt_eaton	4372d 02h	/socgen/trunk/Makefile
113	started refactoring or1200	jt_eaton	4468d 20h	/socgen/trunk/Makefile
112	added more test sims removed unneeded files	jt_eaton	4478d 09h	/socgen/trunk/Makefile
106	checked in orp_soc project step 2	jt_eaton	4502d 02h	/socgen/trunk/Makefile
103	added user guide resynced to local repository	jt_eaton	4527d 00h	/socgen/trunk/Makefile
102	all ip-xact files now readable by kactus2	jt_eaton	4588d 19h	/socgen/trunk/Makefile
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4589d 21h	/socgen/trunk/Makefile
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4602d 05h	/socgen/trunk/Makefile
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4644d 21h	/socgen/trunk/Makefile
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4681d 02h	/socgen/trunk/Makefile
96	hierConnections now create ports	jt_eaton	4754d 23h	/socgen/trunk/Makefile
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4790d 22h	/socgen/trunk/Makefile
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4816d 22h	/socgen/trunk/Makefile
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4914d 04h	/socgen/trunk/Makefile
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4928d 22h	/socgen/trunk/Makefile
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	4997d 04h	/socgen/trunk/Makefile
57	Now generate all filelists from xml files	jt_eaton	5030d 00h	/socgen/trunk/Makefile
56	soc_builder now builds verilog from xml files	jt_eaton	5035d 08h	/socgen/trunk/Makefile
54	now set up fpga targets from xml files	jt_eaton	5038d 06h	/socgen/trunk/Makefile

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[/] [socgen/] [trunk/] [Makefile] - Rev 134

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