OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk] - Rev 128

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools		 jt_eaton 4015d 04h /socgen/trunk
127 final cleanup before DAC jt_eaton 4130d 00h /socgen/trunk
126 added mor1kx
cleanup		 jt_eaton 4183d 05h /socgen/trunk
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control		 jt_eaton 4227d 23h /socgen/trunk
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem		 jt_eaton 4281d 02h /socgen/trunk
123 added support for ubuntu 12.10 jt_eaton 4295d 18h /socgen/trunk
122 Moved Nexys2 from opencores.org to digilentinc.com
Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components		 jt_eaton 4303d 21h /socgen/trunk
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code		 jt_eaton 4324d 03h /socgen/trunk
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench		 jt_eaton 4342d 03h /socgen/trunk
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace		 jt_eaton 4376d 22h /socgen/trunk
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs		 jt_eaton 4412d 07h /socgen/trunk
117 added yellow pages tools jt_eaton 4440d 02h /socgen/trunk
116 added build_header
now use build_register for all spr components
resynced or1200 code back to use orbuild toolchain		 jt_eaton 4474d 23h /socgen/trunk
115 split or1200_cpu up into all ip-xact components
removed dead files		 jt_eaton 4519d 03h /socgen/trunk
114 moved or1200 connectivity out of verilog and into ip-xact
added or1200_boot block
removed force of 00 on lowest iwb_addr bits		 jt_eaton 4531d 03h /socgen/trunk
113 started refactoring or1200 jt_eaton 4536d 19h /socgen/trunk
112 added more test sims
removed unneeded files		 jt_eaton 4546d 08h /socgen/trunk
111 split or1200 out into seperate test suite jt_eaton 4548d 02h /socgen/trunk
110 split out more ip-xact components
added sw sources		 jt_eaton 4560d 00h /socgen/trunk
109 removed unused file jt_eaton 4563d 00h /socgen/trunk
108 removed unneeded files jt_eaton 4564d 06h /socgen/trunk
107 added designCfg files to all modules jt_eaton 4564d 09h /socgen/trunk
106 checked in orp_soc project step 2 jt_eaton 4570d 02h /socgen/trunk
105 moved or1200_monitor from testbench to dut jt_eaton 4572d 22h /socgen/trunk
104 fixed search in preprocessor script
added initial orp_soc project		 jt_eaton 4574d 23h /socgen/trunk
103 added user guide
resynced to local repository		 jt_eaton 4594d 23h /socgen/trunk
102 all ip-xact files now readable by kactus2 jt_eaton 4656d 19h /socgen/trunk
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4657d 20h /socgen/trunk
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4670d 04h /socgen/trunk
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4712d 21h /socgen/trunk

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.