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[/] [spacewiresystemc/] - Rev 26

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Rev	Log message	Author	Age	Path
26	Adding write axi and updating files.	redbear	2577d 06h	/spacewiresystemc
25	Updating	redbear	2577d 06h	/spacewiresystemc
24	Removing altera quartus 16.0	redbear	2577d 06h	/spacewiresystemc
23	FPGA verilog and corrections.	redbear	2606d 06h	/spacewiresystemc
22	Adding files work to altera fpga DE0 NANO SOC.	redbear	2606d 07h	/spacewiresystemc
21	Vpi data rx.	redbear	2627d 06h	/spacewiresystemc
20	SystemC minor correction.	redbear	2627d 06h	/spacewiresystemc
19	RX and TX correct.	redbear	2627d 06h	/spacewiresystemc
18	FSM minor correction	redbear	2634d 05h	/spacewiresystemc
17	TX correction FCT reaceive and TX data transfer.	redbear	2634d 05h	/spacewiresystemc
16	Adding TX_WRITE to go down after detect first edge posedge tx_ready.	redbear	2634d 05h	/spacewiresystemc
15	Tx with FCT with partial correction.	redbear	2662d 06h	/spacewiresystemc
14	New version of Receiver.	redbear	2662d 06h	/spacewiresystemc
13	upating files.	redbear	2689d 06h	/spacewiresystemc
12	update files and SystemC.	redbear	2711d 07h	/spacewiresystemc
11	Adding shared object.	redbear	2721d 07h	/spacewiresystemc
10	Update tx verilog rx systemc test.	redbear	2721d 07h	/spacewiresystemc
9	Update shared object and Graphical interface.	redbear	2721d 07h	/spacewiresystemc
8	EOPDATA is functional.	redbear	2721d 07h	/spacewiresystemc
7	Updating testbench file using correcting signals VPI.	redbear	2726d 09h	/spacewiresystemc
6	Updating FCT and NCHAR counters on TX.	redbear	2726d 09h	/spacewiresystemc
5	Adding first verilog with new struct dir.	redbear	2738d 08h	/spacewiresystemc
4	Deleting all	redbear	2738d 08h	/spacewiresystemc
3	Adding a tutorial about the use of SpaceWire Test Suit.	redbear	2903d 13h	/spacewiresystemc
2	initial work with spacewire	redbear	2911d 21h	/spacewiresystemc
1	The project and the structure was created	root	2912d 12h	/spacewiresystemc

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Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] - Rev 26

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