URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] - Rev 345

Rev	Log message	Author	Age	Path
345	remove trunk after tagging rel_1_4	arniml	497d 17h	/t48
344	release 1.4	arniml	497d 17h	/t48
343	branch wip_t2x merged into trunk at 342	arniml	497d 17h	/t48
342	merge branch wip_t2x into trunk	arniml	497d 17h	/t48
341	interrupt test for 8022	arniml	520d 20h	/t48
340	adapt int tests to ALE sampling	arniml	520d 20h	/t48
339	fix RETI for 8022	arniml	520d 20h	/t48
338	sample int with rising ALE	arniml	520d 20h	/t48
337	t8022 synthesis	arniml	520d 22h	/t48
336	docs	arniml	520d 23h	/t48
335	simplify up41 test setup	arniml	521d 02h	/t48
334	fix timing of sel_an*, rad	arniml	521d 13h	/t48
333	add t8022	arniml	521d 19h	/t48
332	mcs2x tests	arniml	522d 15h	/t48
331	release 1.3	arniml	522d 21h	/t48
330	add t8021	arniml	522d 21h	/t48
329	start work on t2x	arniml	523d 15h	/t48
328	prepare 1.3	arniml	525d 17h	/t48
327	update integration manual	arniml	526d 14h	/t48
326	refine status_q update	arniml	526d 19h	/t48
325	experimental upi41_db_bus variant with asynchronous master interface	arniml	527d 02h	/t48
324	enhance access timing in test bench	arniml	527d 02h	/t48
323	- prevent change when master reads status - relax master access timing	arniml	528d 01h	/t48
322	hold db_dir_o during entire access	arniml	529d 16h	/t48
321	improve compatibility with modelsim and ghdl	arniml	530d 14h	/t48
320	improve in test	arniml	530d 14h	/t48
319	- add dma test - update dma logic	arniml	532d 16h	/t48
318	t8042ah synth, fix warnings	arniml	532d 21h	/t48
317	implement dma logic	arniml	532d 22h	/t48
316	doc	arniml	533d 02h	/t48