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[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 292

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292 New directory structure. root 5665d 13h /t48/tags/rel_0_5_beta
255 This commit was manufactured by cvs2svn to create tag 'rel_0_5_beta'. 6635d 22h /tags/rel_0_5_beta
147 initial check-in for release 0.5 BETA arniml 7261d 01h /trunk
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7262d 01h /trunk
145 remove PROG and end of XTAL2, see comment for details arniml 7262d 02h /trunk
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7262d 02h /trunk
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7262d 03h /trunk
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7262d 03h /trunk
141 disable external memory to avoid conflicts with outl a, bus arniml 7262d 03h /trunk
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7262d 03h /trunk
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7263d 13h /trunk
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7263d 13h /trunk
137 add link to COMPILE_LIST arniml 7301d 02h /trunk
136 initial check-in arniml 7301d 02h /trunk
135 add bug
PSENn Timing		 arniml 7305d 12h /trunk
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7305d 22h /trunk
133 add checks for PSEN arniml 7305d 22h /trunk
132 stop simulation upon assertion error arniml 7305d 22h /trunk
131 update arniml 7305d 22h /trunk
130 initial check-in arniml 7305d 22h /trunk
129 cleanup copyright notice arniml 7368d 06h /trunk
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7375d 10h /trunk
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7375d 11h /trunk
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7375d 11h /trunk
125 exclude from dump compare arniml 7375d 11h /trunk
124 fix wrong handling of MB after return from interrupt arniml 7376d 08h /trunk
123 support hex file for external ROM arniml 7376d 08h /trunk
122 test MB after return from interrupt arniml 7376d 08h /trunk
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7379d 01h /trunk
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7379d 01h /trunk

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