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[/] [t48/] [tags/] [rel_1_0] - Rev 169

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Rev Log message Author Age Path
169 initial check-in arniml 7009d 07h /t48/tags/rel_1_0
168 change address range of wb_master arniml 7009d 07h /t48/tags/rel_1_0
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7009d 07h /t48/tags/rel_1_0
166 assign default for state_s arniml 7010d 23h /t48/tags/rel_1_0
165 add component wb_master.vhd arniml 7011d 22h /t48/tags/rel_1_0
164 initial check-in arniml 7011d 22h /t48/tags/rel_1_0
163 add bug
Wrong clock applied to T0		 arniml 7012d 22h /t48/tags/rel_1_0
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7012d 22h /t48/tags/rel_1_0
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7044d 02h /t48/tags/rel_1_0
160 add others to case statement arniml 7164d 22h /t48/tags/rel_1_0
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7164d 22h /t48/tags/rel_1_0
158 added hierarchies t8039_notri and t8048_notri arniml 7164d 22h /t48/tags/rel_1_0
157 removed obsolete constant arniml 7164d 22h /t48/tags/rel_1_0
156 added hierarchy t8039_notri arniml 7164d 22h /t48/tags/rel_1_0
155 initial check-in arniml 7164d 22h /t48/tags/rel_1_0
154 added t8039_notri hierarchy arniml 7164d 22h /t48/tags/rel_1_0
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7165d 20h /t48/tags/rel_1_0
152 added hierarchy t8048_notri and system components package arniml 7166d 11h /t48/tags/rel_1_0
151 added hierarchy t8048_notri and components package for t48 systems arniml 7166d 11h /t48/tags/rel_1_0
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7166d 19h /t48/tags/rel_1_0
149 update arniml 7166d 19h /t48/tags/rel_1_0
148 initial check-in arniml 7166d 19h /t48/tags/rel_1_0
147 initial check-in for release 0.5 BETA arniml 7202d 20h /t48/tags/rel_1_0
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7203d 20h /t48/tags/rel_1_0
145 remove PROG and end of XTAL2, see comment for details arniml 7203d 21h /t48/tags/rel_1_0
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7203d 22h /t48/tags/rel_1_0
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7203d 22h /t48/tags/rel_1_0
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7203d 22h /t48/tags/rel_1_0
141 disable external memory to avoid conflicts with outl a, bus arniml 7203d 22h /t48/tags/rel_1_0
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7203d 22h /t48/tags/rel_1_0

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