OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0] - Rev 213

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
213 properly drive P1 and P2 with low impedance markers arniml 6830d 08h /t48/tags/rel_1_0
212 add bug reports
"Problem when INT and JMP"
"P2 Port value restored after expander access"		 arniml 6830d 11h /t48/tags/rel_1_0
211 wire signals for P2 low impedance marker issue arniml 6831d 11h /t48/tags/rel_1_0
210 entity changes for P2 low impedance marker issue arniml 6831d 11h /t48/tags/rel_1_0
209 entity changes for P2 low impedance issue arniml 6831d 11h /t48/tags/rel_1_0
208 wire signals for P2 low impeddance marker issue arniml 6831d 11h /t48/tags/rel_1_0
207 entity changes for P2 low impedance trigger issue arniml 6831d 11h /t48/tags/rel_1_0
206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads		 arniml 6831d 11h /t48/tags/rel_1_0
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6831d 11h /t48/tags/rel_1_0
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module		 arniml 6831d 11h /t48/tags/rel_1_0
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8		 arniml 6831d 11h /t48/tags/rel_1_0
202 fix address assignment arniml 6831d 11h /t48/tags/rel_1_0
201 split low impedance markers for P2 arniml 6831d 11h /t48/tags/rel_1_0
200 add check for
tCP: Port Control Setup to PROG'		 arniml 6831d 11h /t48/tags/rel_1_0
199 initial check-in arniml 6831d 11h /t48/tags/rel_1_0
198 fix package dependencies arniml 6831d 15h /t48/tags/rel_1_0
197 preliminary version 0.3 arniml 6832d 18h /t48/tags/rel_1_0
196 update to version 0.3 arniml 6832d 18h /t48/tags/rel_1_0
195 Suppress assertion of bus_read_bus_s when interrupt is pending.
This should fix bug report
"PROBLEM WHEN INT AND JMP"		 arniml 6832d 22h /t48/tags/rel_1_0
194 initial check-in arniml 6832d 22h /t48/tags/rel_1_0
193 iManual arniml 6848d 00h /t48/tags/rel_1_0
192 update list for Wishbone toplevel arniml 6848d 11h /t48/tags/rel_1_0
191 preliminary version 0.2 arniml 6848d 14h /t48/tags/rel_1_0
190 finalize change log for release 0.6 beta arniml 6849d 09h /t48/tags/rel_1_0
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"		 arniml 6880d 11h /t48/tags/rel_1_0
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6880d 11h /t48/tags/rel_1_0
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6880d 11h /t48/tags/rel_1_0
186 update to version 0.2 arniml 6881d 12h /t48/tags/rel_1_0
185 initial check-in arniml 6886d 10h /t48/tags/rel_1_0
184 initial check-in arniml 6886d 12h /t48/tags/rel_1_0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.