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[/] [t48/] [tags/] [rel_1_0] - Rev 226

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226 replaced syn_ram with generic_ram_ena arniml 6629d 16h /t48/tags/rel_1_0
225 replaced syn_rom and syn_ram with t48_rom and generic_ram_ena arniml 6629d 16h /t48/tags/rel_1_0
224 initial check-in arniml 6629d 16h /t48/tags/rel_1_0
223 obsoleted arniml 6629d 16h /t48/tags/rel_1_0
222 add note about clock enable for data memory RAM macro arniml 6630d 16h /t48/tags/rel_1_0
221 new input xtal_en_i arniml 6630d 16h /t48/tags/rel_1_0
220 new input xtal_en_i arniml 6630d 16h /t48/tags/rel_1_0
219 new input xtal_en_i gates xtal_i base clock arniml 6630d 16h /t48/tags/rel_1_0
218 simplifications arniml 6717d 00h /t48/tags/rel_1_0
217 update for release 0.6.1 beta arniml 6785d 20h /t48/tags/rel_1_0
216 assign clk_i to outclock arniml 6847d 20h /t48/tags/rel_1_0
215 suppress p2_output_pch_o when MOVX operation is accessing the
external memory		 arniml 6847d 20h /t48/tags/rel_1_0
214 fix sensitivity list arniml 6854d 22h /t48/tags/rel_1_0
213 properly drive P1 and P2 with low impedance markers arniml 6859d 17h /t48/tags/rel_1_0
212 add bug reports
"Problem when INT and JMP"
"P2 Port value restored after expander access"		 arniml 6859d 20h /t48/tags/rel_1_0
211 wire signals for P2 low impedance marker issue arniml 6860d 19h /t48/tags/rel_1_0
210 entity changes for P2 low impedance marker issue arniml 6860d 19h /t48/tags/rel_1_0
209 entity changes for P2 low impedance issue arniml 6860d 19h /t48/tags/rel_1_0
208 wire signals for P2 low impeddance marker issue arniml 6860d 20h /t48/tags/rel_1_0
207 entity changes for P2 low impedance trigger issue arniml 6860d 20h /t48/tags/rel_1_0
206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads		 arniml 6860d 20h /t48/tags/rel_1_0
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6860d 20h /t48/tags/rel_1_0
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module		 arniml 6860d 20h /t48/tags/rel_1_0
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8		 arniml 6860d 20h /t48/tags/rel_1_0
202 fix address assignment arniml 6860d 20h /t48/tags/rel_1_0
201 split low impedance markers for P2 arniml 6860d 20h /t48/tags/rel_1_0
200 add check for
tCP: Port Control Setup to PROG'		 arniml 6860d 20h /t48/tags/rel_1_0
199 initial check-in arniml 6860d 20h /t48/tags/rel_1_0
198 fix package dependencies arniml 6861d 00h /t48/tags/rel_1_0
197 preliminary version 0.3 arniml 6862d 03h /t48/tags/rel_1_0

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