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[/] [t48/] [tags/] [rel_1_1/] - Rev 226

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226 replaced syn_ram with generic_ram_ena arniml 6597d 20h /t48/tags/rel_1_1
225 replaced syn_rom and syn_ram with t48_rom and generic_ram_ena arniml 6597d 20h /t48/tags/rel_1_1
224 initial check-in arniml 6597d 20h /t48/tags/rel_1_1
223 obsoleted arniml 6597d 20h /t48/tags/rel_1_1
222 add note about clock enable for data memory RAM macro arniml 6598d 20h /t48/tags/rel_1_1
221 new input xtal_en_i arniml 6598d 20h /t48/tags/rel_1_1
220 new input xtal_en_i arniml 6598d 21h /t48/tags/rel_1_1
219 new input xtal_en_i gates xtal_i base clock arniml 6598d 21h /t48/tags/rel_1_1
218 simplifications arniml 6685d 04h /t48/tags/rel_1_1
217 update for release 0.6.1 beta arniml 6754d 00h /t48/tags/rel_1_1
216 assign clk_i to outclock arniml 6816d 00h /t48/tags/rel_1_1
215 suppress p2_output_pch_o when MOVX operation is accessing the
external memory		 arniml 6816d 00h /t48/tags/rel_1_1
214 fix sensitivity list arniml 6823d 02h /t48/tags/rel_1_1
213 properly drive P1 and P2 with low impedance markers arniml 6827d 22h /t48/tags/rel_1_1
212 add bug reports
"Problem when INT and JMP"
"P2 Port value restored after expander access"		 arniml 6828d 00h /t48/tags/rel_1_1
211 wire signals for P2 low impedance marker issue arniml 6829d 00h /t48/tags/rel_1_1
210 entity changes for P2 low impedance marker issue arniml 6829d 00h /t48/tags/rel_1_1
209 entity changes for P2 low impedance issue arniml 6829d 00h /t48/tags/rel_1_1
208 wire signals for P2 low impeddance marker issue arniml 6829d 00h /t48/tags/rel_1_1
207 entity changes for P2 low impedance trigger issue arniml 6829d 00h /t48/tags/rel_1_1
206 * change low impedance markers for P2
separate marker for low and high part
* p2_o output is also registered to prevent combinational
output to pads		 arniml 6829d 00h /t48/tags/rel_1_1
205 operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3 arniml 6829d 00h /t48/tags/rel_1_1
204 * suppress p2_output_pch_o when p2_output_exp is active
* wire xtal_i to interrupt module		 arniml 6829d 00h /t48/tags/rel_1_1
203 * shift assertion of ALE and PROG to xtal3
* correct change of revision 1.8		 arniml 6829d 00h /t48/tags/rel_1_1
202 fix address assignment arniml 6829d 00h /t48/tags/rel_1_1
201 split low impedance markers for P2 arniml 6829d 00h /t48/tags/rel_1_1
200 add check for
tCP: Port Control Setup to PROG'		 arniml 6829d 00h /t48/tags/rel_1_1
199 initial check-in arniml 6829d 00h /t48/tags/rel_1_1
198 fix package dependencies arniml 6829d 05h /t48/tags/rel_1_1
197 preliminary version 0.3 arniml 6830d 08h /t48/tags/rel_1_1

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