OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1] - Rev 116

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7348d 08h /t48/tags/rel_1_1
115 extend description arniml 7349d 12h /t48/tags/rel_1_1
114 initial check-in arniml 7353d 08h /t48/tags/rel_1_1
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7359d 17h /t48/tags/rel_1_1
112 update tb_behav_c0 for new ROM layout arniml 7359d 17h /t48/tags/rel_1_1
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7359d 17h /t48/tags/rel_1_1
110 exchange syn_rom for lpm_rom arniml 7359d 17h /t48/tags/rel_1_1
109 add new bug for release 0.1 BETA arniml 7360d 07h /t48/tags/rel_1_1
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7360d 07h /t48/tags/rel_1_1
107 tie EA to '1' arniml 7360d 07h /t48/tags/rel_1_1
106 clean-up use of ea_i arniml 7360d 07h /t48/tags/rel_1_1
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7362d 17h /t48/tags/rel_1_1
104 add white_box directory to test suite arniml 7363d 14h /t48/tags/rel_1_1
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7363d 14h /t48/tags/rel_1_1
102 update for changes in address space of external memory arniml 7363d 14h /t48/tags/rel_1_1
101 assert p2_read_p2_o when expander port is read arniml 7363d 14h /t48/tags/rel_1_1
100 reorder data_o generation arniml 7363d 14h /t48/tags/rel_1_1
99 initial check-in arniml 7363d 14h /t48/tags/rel_1_1
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7363d 15h /t48/tags/rel_1_1
97 initial check-in arniml 7363d 15h /t48/tags/rel_1_1
96 select dedicated directorie(s) for regression arniml 7364d 12h /t48/tags/rel_1_1
95 check counter inactivity arniml 7364d 12h /t48/tags/rel_1_1
94 initial check-in arniml 7364d 12h /t48/tags/rel_1_1
93 add support for line coverage evaluation with gcov arniml 7364d 13h /t48/tags/rel_1_1
92 work around bug in Quartus II 4.0 arniml 7364d 13h /t48/tags/rel_1_1
91 fix edge detector bug for counter arniml 7364d 13h /t48/tags/rel_1_1
90 intial check-in arniml 7364d 13h /t48/tags/rel_1_1
89 initial check-in arniml 7378d 09h /t48/tags/rel_1_1
88 allow memory bank switching during interrupts arniml 7379d 11h /t48/tags/rel_1_1
87 abort gracfullt if memory bank switching does not work arniml 7379d 11h /t48/tags/rel_1_1

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.